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TA1360AFG
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1360AFG
YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV
The TA1360AFG integrates an analog component signal (YCbCr/YPbPr) processor and sync processor in a 80-pin QFP plastic package. The IC is ideal for digital TVs, progressive TVs, and double scan TVs. The luminance block and the color difference block incorporate the high performance signal processing circuits. The sync processor block supports 525I/60, 625I/50, 525P/60, 625P/50, 1125I/50, 1125I/60, 750P/60, (750P/50), PAL100 Hz, NTSC120 Hz, and SVGA/60(VESA). The TA1360AFG incorporates the I2C bus. The device can control various functions via the bus line.
Weight: 1.6 g (typ.)
Features
Luminance Block
* * * * * * * * * * * * * * * * * * * * * * * Black stretch circuit and DC restoration rate correction circuit Dynamic correction circuit (gray scale correction) SRT (LTI) Y group delay correction (shoot balance correction) High-bright color circuit Color detail enhancer (CDE) White pulse limiter (WPL) VSM output Fresh color correction Dynamic Y/C correction circuit Color SRT (CTI) Color circuit Green stretch Blue stretch OSD blending SW ACB (only black level) Two analog RGB inputs Horizontal sync (15.75 k, 28.125 k, 31.5 k, 33.75 k, 37.9 k, 45 kHz) Vertical sync (525I/P, 625I/P, 750P, 1125I/P, PAL 100 Hz/NTSC 120 Hz 2- and 3-level sync separator circuit HD/VD input (positive and negative polarities) Copy guard Vertical blanking
Color difference Block
Text Block
Synchronization Block
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TA1360AFG
Block Diagram
DEF/DAC GND DEF/DAC VCC
Cb1/Pb1 IN
Cr1/Pr1 IN
Cb2/Pb2 IN 61
I2L GND
I2L VDD
45 Y/C VCC 75 Y/C GND 65 RGB VCC 16 RGB GND 10 SCL 30
38
31
27
68
67
66
63
60
CLAMP CP1 SW YHDPbPr/YCbCr U V UV IQ CONVERTER I CBUS DECODER SW DAC2
2
CLAMP
YUV CONVERT Y BLACK STRETCH BLACK LEVEL CORECTION DYNAMIC LIGHT DET DC REST SHARPNESS DELAY LINE SRT GROUP DELAY + CORRECTION SHARPNESS CONTROL APL DETECT 74 APL FILTER BLACK PEAK DETECT 70 BPH FILTER
SDA 28 DAC2 23 (ACB PLUSE) DAC1 (SYNC OUT) 34 CP OUT 47 SCP IN 49 H-OUT 37 H-FREQ SW1 55 H-FREQ SW2 41 HVCO 42
FRESH COLOR IQ UV CONVERTER SW SYNC OUT Y/C LEVEL COMP CP/BPP H DUTY EXT BPP BPP SW GREEN STRETCH TINT DL/ COLOR SRT CP SW CP1 COLOR + H-BPP V-BPP
Cr2/Pr2 IN
Y1 IN
Y2 IN
DARK DET
71 DARK AREA DET FILTER LIGHT AREA 64 DET FILTER
SW DAC1
H FREQUENCY SW HORIZONTAL PHASE
EXT CP H C/D HVCO CP2 CLAMP PULSE
+ SUBCONTRAST UNICOLOR
Y DETAIL CONTROL CDE
AFC FILTER 44 H CURVE CORRECTION H CURVE 40 CORRECTION FBP IN 39
H-AFC
UNI-COLOR CP2 RELATIVE PHASE/ AMPLITUDE G-Y MATRIX B-Y R-Y G-Y COLOR
CLAMP WPL
BRIGHTNESS ABCL AMP
FBP/BLK
H-RAMP
2 x fH V C/D V FREQUENCY SW ACB PULSE EXT V-BLK
78 ABCL IN
VP OUT 35
VP OUT CLAMP PULSE
WPS HI-BRIGHT COLOR Yout- HALF TONE /Y MUTE COLOR PEAK DETECT HPF 58 COLOR LIMITER
SYNC IN 53
SYNC SEPA HD IN SW
HD IN 50
HD POLARITY
H-BLK
+
V-BLK
HALF TONE /C MUTE
V INTEGRAL
V-CLP WP BLUE CP2
VSM AMP VSM MUTE 57 VSM FILTER 77 VSM OUT 18 ANALOG OSD R IN 19 ANALOG OSD G IN 21 ANALOG OSD B IN 80 YS1 (ANALOG OSD)
VD IN 52 R OUT 12 G OUT 13 B OUT 14
VD IN SW CP2 RGB OUT BLK CLAMP DRIVE BLUE STRETCH CP2 SW S/H CUT OFF RGB BRIGHTNESS IK
CLAMP OSD AMP CP2 MIXER SW/ BLUE BACK OSD ACL SW CLAMP OR
RGB MATRIX
Y
CLAMP
YM SW
1 YS2 (ANALOG OSD)
RGB CONTRAST 4 R S/H 6 G S/H 7 B S/H 24 ANALOG R IN 25 ANALOG G IN 26 ANALOG B IN 2 YS3 (ANALOG RGB) 79 YM/PMUTE/BLK
8 IK IN
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TA1360AFG
Pin Assignment
80 YS1 (ANALOG OSD) 79 YM/PMUTE/BLK 78 ABCL IN 77 VSM OUT 76 NC 75 Y/C VCC 74 APL FILTER 73 NC 72 NC 71 DARK AREA DET FILTER 70 BPH FILTER 69 NC 68 Y1 IN 67 Cb1/Pb1 IN 66 Cr1/Pr1 IN 65 Y/C GND Y2 IN 63 NC 62 Cb2/Pb2 IN 61 Cr2/Pr2 IN 60 NC 59 COLOR LIMITER 58 VSM FILTER 57 NC 56 H-FREQ SW1 55 NC 54 SYNC IN 53 TA1360AFG 13 G OUT 14 B OUT 15 NC 16 RGB VCC 17 NC 18 ANALOG OSD R IN 19 ANALOG OSD G IN 20 NC 21 ANALOG OSD B IN 22 NC 23 DAC2 (ACB PULSE) DAC1 (SYNC OUT) 24 ANALOG R IN ANALOG G IN ANALOG B IN I2L GND DEF/DAC GND VD IN 52 NC 51 HD IN 50 SCP IN 49 NC 48 CP OUT 47 NC 46 DEF/DAC VCC 45 AFC FILTER 44 NC 43 HVCO 42 H COURVE CORRECTION 40 H-FREQUENCY SW2 41
1 YS2 (ANALOG OSD) 2 YS3 (ANALOG RGB)
LIGHT AREA 64 DET FILTER
3 NC 4 R S/H 5 NC 6 G S/H 7 B S/H 8 IK IN 9 NC 10 RGB GND 11 NC 12 R OUT
VP OUT
I2L VDD
SDA
SCL
25
26
27
28
29
NC
30
31
32
33
34
35
36
37
38
39
FBP IN
H-OUT
NC
NC
NC
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TA1360AFG
Pin Functions
Pin No. Pin Name Function Switches internal RGB and OSD input signals. The blend ratio of internal RGB and OSD signals can be adjusted according to applying voltage to pins YS1 and YS2. 1 YS2 (analog OSD) VSM output is muted when YS1 or YS2 pin is set to High. YS2 YS1 80 YS1 (analog OSD) L H L H L L H H Blend ratio Int RGB: OSD RGB 10:0 7:3 5:5 0:10 1 80 300 50 k 16 Interface Circuit Input Signal/Output Signal
0 to 0.5 V
: Internal
1.1 V to 1.7 V : VSM Mute 2.9 V to 9 V 10 : OSD, VSM Mute
16 Switches internal RGB and external analog RGB input. VSM output is muted when analog RGB is selected. 2 300 50 k 300 0 to 0.5 V : Internal
2
YS3 (analog RGB)
1.5 V to 9 V : Analog RGB, VSM Mute 10
This pin is not used. 3 NC Connect to GND.
16
4
R S/H S/H (sample-and-hold) pin. 4 6 7
500 1 k 5 k DC 3 pF 3V 10
6
G S/H
In ACB Mode, connect 2.2-F capacitor. In CUT-OFF Mode, connect 0.01-F capacitor.
7
B S/H
This pin is not used. 5 NC Connect to GND.
16 Inputs feedback signal from CRT. (BLK level should be 0 to 3 V.) 8 IK IN When ACB function is not used, connect this pin to RGB VCC pin. 8 1 Vp-p (typ.) R 1 k 0~3 V G B
or RGB VCC 10
This pin is not used. 9 10 11 NC Connect to GND. RGB GND NC Connect to GND. GND pin for text/RGB block This pin is not used.

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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
16 12 R OUT Outputs R/G/B signal. 13 G OUT Recommended output amplitude: 100 IRE = 2.3 Vp-p 12 13 14 200 100 100 IRE: 2.3 Vp-p Conditions: UNI-COLOR = max SUB-CONT = Cent 2.5 mA Y IN = 0.7 Vp-p 10
14
B OUT
This pin is not used. 15 NC Connect to GND. VCC pin for text/RGB block. 16 RGB VCC See "Maximum Ratings" about the supply voltage. This pin is not used. 17 NC Connect to GND.

16 18 ANALOG OSD R IN 18 19 21 1 k 1 k 100 IRE: 0.7 Vp-p (not including sync)
19
ANALOG OSD G IN
Inputs analog OSD signal via clamp capacitor.
21
ANALOG OSD B IN
1 k
10
20 NC 22
This pin is not used. Connect to GND.
16 DC or ACB PULSE DAC2 (ACB pulse) Outputs 1-bit DAC or pulse over ACB period. Open-collector output. 500
23
23
10
16 24 ANALOG R IN Inputs analog R/G/B signal via clamp capacitor. 24 25 26 1 k 1 k 100 IRE: 0.7 Vp-p (not including sync)
25
ANALOG G IN
26
ANALOG B IN
1 k
10 I2L GND GND pin for I2L block
27
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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
45
ACK
2.25 V
28
SDA
SDA pin for I2C BUS
28
50
5 k
SDA
38 27
This pin is not used. 29 NC Connect to GND.
45
2.25 V
30
SCL
SCL pin for I2C BUS
30
5 k
SCL
38 27 VDD pin for I2L block. Connects 2 V (typ.). 31 I2L VDD Supply power via zener diode through resistor from pin 45. (See "Application Circuit") This pin is not used. NC 33 Connect to GND.
32
45 Outputs 1-bit DAC or separated SYNC. Open-collector output. 27 38 500 DC or SYNC OUT
34
DAC1 (SYNC OUT)
34
45 200 A Outputs vertical pulse. Applying current to this pin, performs external blanking by OR-ing with internal blanking. Note: Changing H-position varies VP output width. Use the start phase only for VP output. 200
VP output: 5V
35
VP OUT
35
0V 27 Start phase 38 V-BLK input current: 780 A to 1 mA
This pin is not used. 36 NC Connect to GND.
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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
45
37
H-OUT
Horizontal output pin. Open-collector output.
37
5 k
38
38
DEF/DAC GND
GND pin for DEF/DAC block
45
2.25 V
max: 9 V H-AFC threshold : 5.3 V BLK threshold : 2.3 V
Inputs FBP for horizontal AFC. 39 FBP IN Sets H-BLK width. 39 500 30 k 5V 20 k
38
45 Adjusts screen curve at high voltage fluctuation. Input AC component of high voltage fluctuation. When not used, connect 0.01-F capacitor between this pin and GND. 65 k 50 k
40
H CURVE CORRECTION
40
1 k
DC 25 k 6.5 V 130 k
38
45 Switches horizontal frequency (Switch 2). Leave this pin open when horizontal frequency is switched by Bus controlling. Controlling this pin prevails over Bus control. (Refer to Table 1: Bus control function.) When this IC is used for CRT, frequency of horizontal output (pin 37) is controlled according to voltage of this pin. DC voltage that is generated by dividing resistor of DEF VCC (pin 45) should be used to control this pin. 60 k 1 k
60 k 60 k 15 k
41
H-FREQ SW2
41
1 k 30 k
7.5 V
At BUS control (horizontal frequency) : output voltage value 28 k/15 kHz : DC 9 V 31 kHz : DC 6 V 33 kHz : DC 3 V 37 k/45 kHz : DC 0 V At pin 22 control, horizontal frequency and input voltage value 0 to 1.0 V : 37 k/45 kHz 2.0 V to 4.0 V : 33 kHz 5.0 V to 7.0 V : 31 kHz 8.0 V to 9.0 V : 28 k/15 kHz
4.5 V
20 pF
1.5 V 16 k
38
45
2 k
Connects ceramic oscillator for horizontal oscillation. 42 HVCO Use Murata "CSBLA503KECZF30". 42
1 k
1 k 10 k 38
This pin is not used. 43 NC Connect to GND.
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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
45
7.5 k
44 44 AFC FILTER Connects filter for detecting AFC.
300
30 k
VCO DC
6.3 V
38
VCC pin for DEF/DAC block. 45 DEF/DAC VCC See "Maximum Ratings" about the supply voltage. This pin is not used. 46 NC Connect to GND.
45 5V 2.5 k 47 CP OUT Outputs internal clamp pulse (CP). 47 200
0V 38
This pin is not used. 48 NC Connect to GND.
45 Inputs SCP from up converter. Input signals are clamp pulse (CP) and black peak detection stop pulse (BPP). 2.2 V to 2.8 V : BPP 4.2 V to 9 V 50 k : CP
49
SCP IN
49
5 k
38
45
Threshold : 0.75 V 0V
50
HD IN
50 k
Inputs horizontal sync HD signal. Inputs positive- or negative-polarity signals.
50
1 k or
38
Threshold : 0.75 V 0V
This pin is not used. 51 NC Connect to GND.
45
Threshold : 0.75 V 0V
52
VD IN
Inputs vertical sync VD signal. Inputs positive- or negative-polarity signals.
52
1 k or 45 k
38
Threshold : 0.75 V 0V
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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal White 100%: 1 Vp-p 45
1 k Inputs Y signal with sync signal via clamp capacitor. 53 1 k 1 k or
53
SYNC IN
60 k
38
This pin is not used. 54 NC Connect to GND. Switches horizontal frequency (Switch 1).
55
H-FREQ SW1
50 k
Controlling this pin prevails over Bus control. (Refer to Table 1: Bus control function.) When this IC is used for CRT, connect this pin to DEF VCC (pin 45) or DEF GND (pin 38). If it is not necessary to control this pin on CRT, connect this pin directly to DEF VCC or DEF GND on the PCB. This pin is not used.
55
1 k DEF VCC or DEF GND 30 k
50 A
Leave this pin open when horizontal frequency is switched by Bus controlling.
45
38
56
NC Connect to GND.
57 Connects VSM output filter. 57 VSM FILTER Please connect 0.01-F capacitor between this pin and GND. 200
200 1 k
16
DC 1 k 77
1.6 mA 65
16 7 A 58 COLOR LIMITER Connects filter for detecting color limit. 58 5 k DC
65
This pin is not used. 59 NC Connect to GND.
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TA1360AFG
Pin No. 60 61 Pin Name Cr2/Pr2 IN Cb2/Pb2 IN Function Inputs Cr2/Pr2 signal via clamp capacitor. Inputs Cb2/Pb2 signal via clamp capacitor. 16 60 61 63 1 k 1 k Interface Circuit Input Signal/Output Signal 700 mVp-p700 mVp-p at 100% color bar for Cr1/Pr1 700 mVp-p at 100% color bar for Cb1/Pb1 1 Vp-p (including sync) at 100% color bar
5 k 63 Y2 IN Inputs Y2 signal via clamp capacitor. 65 or
This pin is not used. 62 NC Connect to GND.
75
Connects filter for detecting light area. 64 LIGHT AREA DET FILTER Voltage of this pin controls dynamic circuit gain for light area.
64 1 k 100 k
5 k DC
1 k
65 700 mVp-p700 mVp-p at 100% color bar for Cr1/Pr1 700 mVp-p at 100% color bar for Cb1/Pb1 16 66 67 68 1 k 1 k 1 Vp-p (including sync) at 100% color bar
65 66 67
Y/C GND Cr1/Pr1 IN Cb1/Pb1 IN
GND pin for Y/C block Inputs Cr1/Pr1 signal via clamp capacitor. Inputs Cb1/Pb1 signal via clamp capacitor.
5 k 68 Y1 IN Inputs Y1 signal via clamp capacitor. 65 or
This pin is not used. 69 NC Connect to GND.
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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
75 Connects filter for detecting black peak. Voltage of this pin controls black stretch gain. Leaving Y open and setting the test circuit SW 2 = C enable to monitor H/V-BPP (black-stretch-stop pulse) width. 4 k 200 1 k 1 k 70
70
BPH FILTER
DC
1 k
5V
65
75
71
100 k
Connects filter for detecting dark area. DARK AREA DET Voltage of this pin controls FILTER dynamic circuit gain for dark area.
71 1 k
5 k DC
1 k
65
72 NC 73
This pin is not used. Connect to GND.
75 40 k Connects filter for correcting DC restoration rate. 74 APL FILTER Leaving this pin open enables to monitor Y signal after black stretch and dynamic . 74
1 k
1 k
65
VCC pin for Y/C block. 75 Y/C VCC See "Maximum Ratings" about the supply voltage. This pin is not used. 76 NC Connect to GND. Outputs Y signal for VSM that passed through HPF circuit (first differential circuit). Output signals are muted according to pins 1, 2, and 80.
77
VSM OUT
See pin 57.
16
7.05 V
Inputs ABL and ACL signals. 78 ABCL IN Sets gain and start point of ABL and dynamic ABL signal according to bus controlling. 78
30 k
5 k DC
10
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TA1360AFG
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
16 300 80 k
High-speed halftone switch for internal RGB signal. 79 YM/P-MUTE/BLK Enables picture mute and blanking.
79
0 to 0.5 V
: Internal
1.2 V to 1.8 V : Half Tone 2.7 V to 4.0 V : P-Mute 7 V to 9 V : Blanking
10 k
10
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TA1360AFG
Bus Control Map
Write Data
Slave Address: 88H
Sub-Add 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F D-ABL POINT ABL POINT DYNC GAIN OSD BRIGHT BS-CHAR1 OSD CONTRAST R-Y/B-Y GAIN G-Y/B-Y GAIN COLOR SRT TRAN C.D.E. VSM PHASE DC REST POINT BLACK STRETCH POINT SRT-GAIN D-ABL GAIN BL STRETCH POINT ABL GAIN STATIC GAIN-1 Y/C-DL1 BS-CHAR2 Y/C-DL2 C FREQ GREEN STRETCH HI BRT SUB CONTRAST DRIVE GAIN1 DRIVE GAIN2 R CUT OFF G CUT OFF B CUT OFF R-Y/B-Y PHASE G-Y/B-Y PHASE COLOR FLESH CLT H-SHIFT OSD-ACL TINT PICTURE SHARPNESS RGB BRIGHTNESS RGB CONTRAST WPS YUV MODE Y-OUT DR-R DR-B/G ACB-MODE D7 H-FREQ1 D6 D5 H-DUTY D4 YUV-SW D3 DAC1 D2 DAC2 D1 SYNC-SW D0 H-FREQ2 CLP-PHS TEST Preset 1000 1000 1000 1000 1000 1000 1000 1000 HBP-PHS2 BLS DCRR-SW 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
HORIZONTAL POSITION SCP-SW HBP-PHS1 SYNC SEP-LEVEL
V-BLK PHASE COMPRESSION-BLK PHASE-1 P-MODE1
VERTICAL FREQUENCY COMPRESSION-BLK PHASE-2 UNI-COLOR BRIGHTNESS COLOR
Y/C GAIN COMP
BL STRETCH GAIN VSM GAIN DC REST RATE
APACON PEAK FREQ DC REST LIMIT B.L.C. B.D.L WPL-LEVEL P-MODE2 RGB OUT MODE STATIC GAIN-2 DYNC AREA WP BLUE POINT WP BLUE GAIN BS-AREA
APL VS BSP
Y DETAIL CONTROL Y GROUP DELAY CORRECTION
Read Data
Slave Address: 89H
D7 0 POR D6 IK-IN D5 RGB-OUT D4 YUV-IN D3 H-OUT D2 VP-OUT D1 RGB-IN D0 SYNC-IN
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TA1360AFG
Bus Control Features
Write Mode
Resister Name H-FREQ1/2 H-DUTY Description Switches horizontal oscillation frequency. (See the appendix 1) Switches horizontal output duty. 0: 41% 1: 47% Switches YUV input. 0: INPUT-1 (Y1/Cb1/Cr1) 1: INPUT-2 (Y2/Cb2/Cr2) Preset Value 33.75 kHz 41%
YUV-SW
INPUT-1
Switches DAC controlling output. DAC 1 0: OPEN (high) 1: ON (low) Controls 1-bit DAC of open-collector when TEST is 00. Outputs H/C-SYNC from pin 34 when TEST is 01. Switches DAC controlling output. DAC 2 0: ON (low), 1: OPEN (high) ON OPEN
Controls 1-bit DAC of open-collector when TEST is 00. Outputs ACB reference pulse from pin 23 when TEST is 01.
SYNC-SW
Switches sync input. 0: Selects HD/VD input. 1: Selects SYNC input.
HD/VD
Adjusts horizontal picture position (phase). HORIZONTAL POSITION 0000000: -12.5% 1111111: +12.5% CENTER
Note: VP output width (pin 35) varies with a change of horizontal position. Switches clamp pulse phase. 0: 0.7-s (2.5%) width, 1.1-s (3.8%) delay from HD stop phase. CLP-PHS 1: 0.7-s (2.4%) width, 0.2-s (0.7%) delay from HD stop phase when no signal, 0.8-s (2.7%) width that is 1.2-s (4.2%) delay from FBP start phase. Also switches CP phase of CP-OUT (pin 47). Sets ACB mode; Sets converged reference level. ACB MODE 00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE), ACB ON (10 IRE) 1.1-s delay
10: ACB ON (10 IRE) 11: ACB ON (20 IRE) SCP-SW SCP (sand castle pulse) Switches modes. 0: Internal Mode 1: External input Mode Switches phase of black-stretch-detection stop pulse. HBP-PHS1 = 0 and HBP-PHS2 = 0: FBP 3% HBP-PHS1 = 0 and HBP-PHS2 = 1: FBP 8% HBP-PHS1/2 HBP-PHS1 = 1 and HBP-PHS2 = 0: FBP 13% HBP-PHS1 = 1 and HBP-PHS2 = 1: FBP 18% Leaving Y open and setting the test circuit SW2 to C enable to monitor H/V-BPP (black-stretch-detection stop pulse) width through pin 70. SYNC SEP-LEVEL Switches Sync SEP-level. 00: 16% 01: 24% Test Mode: Controls 1-bit DAC of open-collector when TEST is 00. TEST 10: 32% 11: 40% (At 1125I/60)
Internal Mode
3%
16%
Outputs H/C-SYNC from pin 34, and ACB reference pulse from pin 23 when TEST 00 is 01. Do not set TEST to 10/11 for that is shipment TEST Mode.
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Resister Name Switches vertical BLK stop phase. V-BLK PHASE 00000: 16 H~ 11110: 46 H (1 H/STEP) 11111: Internal H/V-BLK OFF Please set ACB Mode to OFF when internal H/V-BLK is OFF (11111). V-FREQUENCY COMPRESSION-BLK PHASE-1/2 P-MODE1/2 UNI-COLOR Vertical free-run frequency: Sets V pull-in range. (See Appendix 2.) Compression BLK phase: Sets BLK for upper and lower parts of screen. (See Appendix 3.) Picture Mode: Sets picture mute, halftone, blue background, and Y mute. (See Appendix 4.) Unicolor adjustment: 0000000: -16dB~ 1111111: 0dB Brightness adjustment: 00000000: -40 IRE OSD-ACL; 0: OFF 1: ON Color adjustment: COLOR 0000000: COLOR MUTE, 0000001: -20dB or more 1111111: +4dB TINT Tint adjustment: 0000000: -32 deg~ 1111111: +32 deg Sharpness adjustment: PICTURE-SHARPNESS 0000000: -10dB or more 1000000: +10dB 1111111: +17.5dB (at peak FREQ) BLS Blue stretch correction: B-axis correction 0: OFF 1: ON RGB brightness: 0000000; -20 IRE~ 1111111; +20 IRE Switches DC restoration rate. 0: 100% or higher 1: 100%or lower High-bright color: 0: OFF 1: ON RGB contrast: 0000000: -16.5dB Sub-contrast: 00000: -3.3dB WPS level: 0: 110 IRE 1: 130 IRE 11111: +2.5dB 1111111: 0dB OFF CENTER 0 deg C-MUTE 11111111: +40 IRE 1281 H CENTER, OFF P-MUTE 1 min 32 H Description Preset Value
BRIGHTNESS
CENTER
OSD-ACL
ON
RGB-BRIGHTNESS
CENTER
DCRR-SW
100% or higher
HI BRT
ON
RGB-CONTRAST
min
SUB-CONTRAST
CENTER
WPS
110 IRE
Y/color-difference input Mode: YUV MODE 0: Y/Cb/Cr, 1: Y/Pb/Pr (Remarks) Y/Cb/Cr: ITU-R BT 601 Y/Pb/Pr: ITU-R BT 709 (1125/60/2:1) Y-out -out gamma control: 0: OFF 1: ON Drive gain 1/2; 0000000: -5dB 1111111: +3dB Switches RGB drive gain base. (See Appendix 5.) OFF Y/Cb/Cr
DRIVE GAIN1/2 DR-R DR-B/G
CENTER R
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Resister Name R/G/B cutoff: 1) At ACB-OFF RGB-OUT R/G/B CUT OFF 00000000: 1.9 V 11111111: 2.9 V CENTER Description Preset Value
2) At ACB-ON SENS-IN 00000000: 0.5 Vp-p 11111111: 1.5 Vp-p R-Y/B-Y GAIN Switches R-Y/B-Y relative amplitude: 0000: min (0.45) 1111: max (0.9) Switches R-Y/B-Y relative phase: 0000: min (90 deg) 1111: max (111.5 deg) Switches G-Y/B-Y relative amplitude: 0000: min (0.25) 1111: max (0.48) Switches G-Y/B-Y relative phase: 0000: min (232 deg) 1111: max (254 deg) Color SRT transient: Color-difference transient improvement 00: C-SRT OFF~ 11: max Color SRT peak frequency: 0: 4.5 MHz Green stretch: 00: OFF~ 11: max (+3dB) Color correction point 00: OFF, 01: 0.23 Vp-p, 10: 0.40 Vp-p, 11: 0.58 Vp-p 1: 5.8 MHz CENTER
R-Y/B-Y PHASE
min
G-Y/B-Y GAIN
CENTER
G-Y/B-Y PHASE
min
COLOR SRT TRAN
CENTER
C FREQ
4.5 MHz
GREEN STRETCH
OFF
COLOR
OFF
CLT
Color limiter level: 0: 1.65 Vp-p, 1: 2 Vp-p Color detail enhancer: 00: min 11: max Dynamic Y/C compensation: Operated when luminance level is made up according to dynamic Y. 00: OFF~ 11: max
1.65 Vp-p
CDE
CENTER
Y/C GAIN COMP
OFF
BL STRETCH GAIN
Blue stretch gain: B-axis correction 00: OFF 11: max (+6.4dB) Flesh color: Skin tone color correction 0: OFF 1: ON (Lead-in angle: 33.7 deg) Shifts a center of horizontal picture position (phase): 0: OFF 1: ON FBP shifts 6.7% against HD VSM phase: 000: -37.5 ns 101: normal VSM gain: 000: OFF 001: 0 dB~ 111: +16dB (VSM gain is limitted 1.4 Vp-p) APACON peak frequency: 00: 13.5 MHz 01: 9.5 MHz 10: 7.2 MHz 11: 4.5 MHz 111: +15 ns
OFF
FLESH
OFF
H-SHIFT
OFF
VSM-PHASE
CENTER
VSM GAIN
OFF
APACON PEAK f0
13.5 MHz
DC REST POINT
DC restoration rate correction point: 000: 0% 111: 49% DC restoration correction rate: 000: 100% 111: 135% (70%) DC restoration rate correction limit point: 00: 67% 01: 77 10: 80% 11: 80%
CENTER
DC REST RATE
min
DC REST LIMIT
min
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Resister Name BLACK STRETCH POINT Black stretch start point 1: 000: OFF 001: 25 IRE~ 111: 55 IRE Black stretch start point 2: 00: 0 IRE 11: 46 IRE up (at APL 100%) Description Preset Value CENTER
APL VS BSP
0 IRE
B.L.C
Black level automatic correction: Up to 6.5 IRE. (Black stretch takes priority.) 0: OFF 1: ON Switches black detection level: 0: 3 IRE 1: 0 IRE
OFF
B.D.L.
3 IRE
BS-AREA
Black stretch area reinforcement: 0: ON 1: OFF SRT gain; Y transient improvement (LTI) 00000: min 11111: max White letters improvement amplitude; 000: min (21 IRE) ~ 110: max (102 IRE) 111: OFF Dynamic ABL detection voltage 00: min 11: max Dynamic ABL sensitivity 00: min 11: max Blue stretch point; B-axis correction 00: min (28 IRE) 11: max (60 IRE) ABL detection voltage 000: min 111: max ABL sensitivity 000: min 111: max RGB output mode; RGB output mode SW for test and adjustment 00: Normal 01: R only 10: G only 11: B only
ON
SRT-GAIN
CENTER
WPL-LEVEL
min
D-ABL POINT
CENTER
D-ABL GAIN
min
BL STRETCH POINT
min
ABL POINT
CENTER
ABL GAIN
min
RGB-OUT MODE
Normal
Dynamic Y gain vs dark area; dynamic -correction according to dark area. DYNC GAIN 00:min~ 11: max (Maximum gain is +6dB included Static Y gain for dark area.) Black stretch characteristic swich BS-CHAR1/2 BS-CHAR1 = 0 and BS-CHAR2 = 0: OFF BS-CHAR1 = 0 and BS-CHAR2 = 1: min BS-CHAR1 = 1 and BS-CHAR2 = 0: mid BS-CHAR1 = 1 and BS-CHAR2 = 1: max Static Y dark area gain; correction for dark area STATIC GAIN-1 000: OFF 001: min (-5dB) ~ 11: max (+2.4dB) Note: When STATIC GAIN-1 is 000(OFF), set DYNC GAIN to min (00), STATIC GAIN-2 to OFF (11), and DYNC AREA to min (000). Static Y light area gain; correction for light area STATIC GAIN-2 00: max (-8.8dB)~ 11: OFF When 00~10 is set, light area static Y and light dynamic Y according to light area is operated. OSD BRIGHT OSD brightness: 00: 5 IRE 01: 0 IRE 10: -5 IRE 11: -10 IRE -5 IRE max OFF OFF CENTER
OSD-CONTRAST
OSD contrast: 00: min (-9.5dB) 11: max (0dB)
min
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Resister Name Description Adjusts Y/C phase; adjusts the phase Y before passing through matrix circuit. Y/C DL1/2 Y/C DL2 = 0 and Y/C DL1 = 0: -10 ns, Y/C DL2 = 0 and Y/C DL1 = 1: -5 ns Y/C DL2 = 1 and Y/C DL1 = 0: 0 ns, Y/C DL2 = 1 and Y/C DL1 = 1: +5 ns DYNCAREA Dynamic dark area detection sensitivity; switches detection sensitivity of dynamic Y of dark area. min 000: min~ 111: max Controls Y detail; corrects sharpness of 5.0-MHz peak frequency. 0000:min (trap) 1111: max +6dB CENTER -10 ns Preset Value
Y DETAIL CONTROL
WP BLUE POINT
White peak blue point; 000: OFF 001: min (42 IRE) ~ 111: max (106 IRE) Y group delay correction; shoot balance correction.
OFF
Y-GROUP DELAY CORRECTION
0000: Pre-shoot gain is lowered. (Overshoot gain is raised.) 1111: Overshoot gain is lowered. (Pre-shoot gain is raised.)
CENTER
WP BLUE GAIN
White peak blue gain. 000: min (+3dB) 111: max (+10dB)
min
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Appendix 1: Horizontal Frequency
Pin Voltages (V) Pin 55 Pin 41 DEF VCC (8.0~9.0) DEF GND (0~1.0) 6.0 (5.0~7.0) 3.0 (2.0~4.0) DEF GND (0~1.0) DEF VCC (8.0~9.0) DEF VCC (8.0~9.0) 6.0 (5.0~7.0) 3.0 (2.0~4.0) DEF GND (0~1.0) 00-D0 0 0 0 0 1 1 1 1 Bus Data 00-D7 0 0 1 1 0 0 1 1 00-D6 0 1 0 1 0 1 0 1 H-Frequency (kHz) 28.125 31.5 33.75 37.9 15.75 31.5 33.75 45
Note 1: Controlling pins prevails over BUS control. When the TA1360F is used for CRT, control horizontal oscillation frequency by pins 41 and 55. (See the pin descriptions for details.) Note 2: Horizontal output frequency may not be switched at once but may takes two steps if switching pins 41 and 55 is controlled at the same time. Switching horizontal output frequency may cause deterioration of the horizontal transistor. Thus, be sure to take account of applications, included software.
Appendix 2; Vertical Frequency
Data 000 001 010 011 100 101 110 111 V Pull-in Range 48~1281 H 48~849 H 48~725 H 48~660 H 48~613 H 48~363 H 48~307 H VP-OUT HI V-BPP Start Phase 1100 H 730 H 600 H 545 H 500 H 290 H 240 H V-BLK P. (C.BLK P.) +20 H Stop Phase Example of Format/V (H)-Frequency 1125P/30 Hz (33.75 kHz) 750P/60 Hz (45 kHz) (750P/50Hz(37.5 kHz)) 625P/50 Hz (31.5 kHz) SVGA/60 Hz(37.9 kHz) 1125I/50 Hz (28.125 kHz) 1125I/60 Hz (33.75 kHz) 525P/60 Hz (31.5 kHz) PAL/SECAM/50 Hz (15.625 kHz), 100 Hz (31.5 kHz) NTSC/60 Hz (15.734 kHz), 120 Hz (31.5 kHz)
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Appendix 3; Compression-BLK Phase
V-Frequency 000 001 010 011 100 101 110 111 Phase-1 (start phase) * 1088 H~1116 H 720 H~748 H 592 H~620 H 528 H~556 H 488 H~516 H 280 H~308 H 224 H~252 H C-BLK OFF 50~78 H (0000: C-BLK2 OFF) Phase-2 (stop phase)
*: C-BLK1 = 1111: C-BLK1 OFF
Appendix 4; P-Mode
05-D7 1A-D1 1A-D0 MODE Description P-Mute and halftone the main signal by pin YM. 0 0 0 NORMAL 1 Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-mute process is executed on Y of main signal by BUS. 0 0 1 Y-MUTE Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-halftone process is executed on main signal by BUS. 0 1 0 YM 1 Insert P-Mute by pin YM, and analog RGB-IN by Ys3. Ys1/Ys2 blends OSD-IN and main halftone signal. Analog RGB-IN > P-Mute Blue background process is executed on main signal by BUS. 0 1 1 BB Insert P-Mute by pin YM, analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2 Analog RGB-IN > P-Mute Full-screen-mute process is executed on main signal by BUS. 1 0 0 P-MUTE 1 Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-halftone process is executed on main signal by BUS. 1 0 1 YM 2 Insert P-Mute by pin YM, and analog RGB-IN by Ys3. Ys1/Ys2 blends OSD-IN and main halftone signal P-Mute > Analog RGB-IN Full-screen-mute process is executed on main signal and analog RGB-IN by BUS. 1 1 0 P-MUTE 2 Insert OSD-IN by Ys1/Ys2. P-Mute > Analog RGB-IN P-Mute and halftone process is executed on the main signal by pin YM. 1 1 1 NORMAL 2 Analog RGB-IN is inserted by Ys3, and OSD-IN by Ys1/Ys2. P-Mute > Analog RGB-IN
Output priority;
(000)~(100): Main signal < BB < P-MUTE < RGB-IN < OSD-IN (101)~(111): Main signal < BB < RGB-IN < P-MUTE < OSD-IN
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Appendix 5; DR-R, DR-B/G
DR-R 0 0 1 1 DR-B/G 0 1 0 1 Reference Axis R R G B Drive Gain1 G G R G Drive Gain2 B B B R
Read Function
Signal Power-on reset: POR 0: RESISTER PRESET 1: Normal Function
After power on, 0 is returned at first read; 1, at second and subsequent reads. IK-IN Detects IK input; detects input through pin 8. 0: NG (no signal) 1: OK (signal detected) Detects RGB-OUT self-check; detects output of pins 12, 13, 14. RGB-OUT 0: NG (no signal) 1: OK (signal detected) Detects signal when all three outputs hsve signals. Small signals are not detected. Detects YUV-IN self-check; detects input of pins 60, 61 63 or pins 66, 67, 68. YUV-IN 0: NG (no signal) 1: OK (signal detected) Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not detected. H-OUT Detects H-OUT self-check; detects output of pin 37. 0: NG (no signal) 1: OK (signal detected) Detects VP-OUT self-check; detects output of pin 35. 0: NG (no signal) 1: OK (signal detected) Detects RGB-IN self-check; detects input of pins 24, 25, 26. RGB-IN 0: NG (no signal) 1: OK (signal detected) Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not detected. SYNC-IN Detects SYNC-IN self-check; detects input of pin 53. 0: NG (no signal), 1: OK (signal detected)
VP-OUT
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How to Transmit/Receive Via I2C Bus
Slave Address: 88H
A6 1 A5 0 A4 0 A3 0 A2 1 A1 0 A0 0 W/R 0/1
Start and Stop Conditions
SDA
SCL S Start condition P Stop condition
Bit Transfer
SDA
SCL
SDA must not be changed
SDA may be changed
Acknowledgement
SDA from transmitter
High impedance at bit 9
SDA from receiver Low impedance only at bit 9 SCL from master S Clock pulse for acknowledgement 1 8 9
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Data Transmit Format 1
S Slave address 7 bit 0A Sub address 8 bit A Transmit data 9 bit MSB P: Stop condition AP
MSB S: Start condition
MSB A: Acknowledgement
Data Transmit Format 2
S Slave address 0A Sub address A Transmit data 1 A A AP
Sub address
Transmit data n
Data Receive Format
S Slave address 7 bit MSB 1A Transmit data 1 8 bit MSB A Receive data 2 AP
To receive data, the master transmitter changes to the receiver immediately after the first acknowledgement. The slave receiver changes to the transmitter. The stop condition is always created by the master. Details are provided in the Philips I2C specifications.
Optional Data Transmit Format
S Slave address 7 bit MSB 0A1 Sub address 7 bit A Transmit data 1 8 bit MSB Transmit data n 8 bit MSB AP
MSB
In this way, sub addresses are automatically incremented from the specified sub address and data are set. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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Maximum Ratings (Ta = 25C)
Characteristics Supply voltage Input pin signal voltage Power dissipation Power dissipation reduction rate depending on temperature Operating temperature Storage temperature Symbol VCCmax einmax PD (Note 3) 1/ja Topr Tstg min Supply voltage (pins 16, 45 and 75) typ. max 8.7 9.0 9.3 -20 to 65 Rating 12 9 2604 20.8 -20 to 70 Unit V Vp-p mW mW/C C C 8.5 8.8 9.1 V
-55 to 150
Note 3: See the following Figure A. (With device mounted on a PCB whose dimensions are 114.3 mm x 76.2 mm x 1.6 mm and whose surface is 20% copper. Mount the device on a PCB of at least these dimensions and whose surface is at least 20% copper.) When using in -25 to 70C of operating temperature, set the IC's power supply voltage (pins 16, 45, 75) to 8.8 V (0.3 V). When designing a set, make sure that the IC can radiate heat because the TA1360AFG has low thermal capacity. Note that the power dissipation varies greatly according to conditions of a board.
2604
Power dissipation PD
(mW)
1771 1667
0 0 25 65 70 150
Ambient temperature Ta (C)
Figure A Power Dissipation Reduction Curve
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Note 4: Power supply sequence At power-on, power should be supplied to the power supply pins according to the following sequence: 1. Pin 31 (I L VDD) 2. Pin 45 (DEF/DAC VCC) 3. Pins 16 and 75 (YC VCC/RGB VCC) Supply power to pin 37 via zener diode through resistor from pin 45. (See "Application Circuit".) BUS preset value is become undefined and caused malfunction of the IC unless supplying power to all supply pins or follow the power supply sequence described above. When the frequency of horizontal output (pin 37) became undefined, horizontal transistor may be damaged. When the TA1360F is used for CRT, control horizontal oscillation frequency by pins 41 and 55.
2
V
DEF/DAC VCC
Horizontal output 6.0 V (typ.)
POR release voltage (BUS operation) 4.6 V (typ.) I2L VDD Logic operation 1.3 V (typ.) t
Figure B
Timing chart that indicates the timing from power-on till horizontal output. (At Ta = 25 C)
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Operating Conditions
Characteristics Pin 16, 45, 75 Supply voltage (VCC) Pin 31 Y input level Color-difference input level HD/VD input level SYNC input level SCP input level Pins 63, 68: 100% color bar, including sync (Picture period amplitude, 0.7 Vp-p) Pins 60, 61 66, 67: 100% color bar, not including sync Pins 50, 52 Pin 53: 100% color bar, including sync CP Pin 49 BPP At 28 k/31 k/33 k/37 kHz Pin 55 At 15 k/31 k/33 k/45 kHz Horizontal frequency switching voltage Pin 41 33.75 kHz 37.9 kHz or 45 kHz H-AFC FBP input level FBP input width H-OUT input current DAC input current SCL/SDA pull-up voltage SDA input current Analog RGB input level Analog OSD input level YS3 switching voltage YS1/2 switching voltage Pin 39 H-BLK Pin 39 Pin 37 Pins 23, 34 Pins 28, 30 Pin 28 Pins 24, 25, 26: White 100% Pins 18, 19, 21: White 100% Pin 2 OSD Pins 1, 80 VSM MUTE BLK YM switching voltage Pin 79 P-MUTE HALF TONE External V-BLK input current Pin 35 1.1 7.0 2.7 1.2 0.78 1.5 VCC 3.5 1.5 3.0 0.16 3.3 1.5 2.9 3.5 9.0 0.3 5.0 0.7 0.7 5.0 5.0 2.0 0 6.5 3.0 0 7.0 4.0 1.0 VCC 4.0 0.3 15.0 mA 1.0 VCC 2 VCC VCC 1.7 V VCC 4.0 1.8 1 mA V mA Vp-p H 28.125 kHz or 15.75 kHz 31.5 kHz 8.0 8.0 5.0 VCC VCC 6.0 VCC VCC 7.0 V 2.2 0 2.5 0 Description Topr = -20 to 65C Topr = -20 to 70C (Note 5) (Note 5) Min 8.7 8.5 1.8 2.0 0.9 4.2 Typ. 9.0 8.8 2.0 1.0 0.7 5.0 1.0 5.0 Max 9.3 9.1 2.2 VCC 1.1 VCC 2.8 1.0 V Vp-p V Unit
Vp-p
Note 5: See "Maximum Ratings" about Topr.
Electrical Characteristics (unless otherwise specified, VCC = 9 V/2 V, Ta = 25C) Current Dissipation
Pin Name DEF/DAC VCC (9 V) RGB VCC (9 V) I L VDD (2 V) Y/C VCC (9 V)
2
Symbol ICC1 ICC2 ICC3 ICC4
Test Circuit
Min 19.2 48.8 21.3 36.8
Typ. 24.0 61.0 25.0 46.0
Max 28.2 67.8 29.4 51.1
Unit
mA
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Pin Voltage
Test Condition
(1) (2) BUS = Preset SW71 = B, SW70 = B, SW68 = C, SW67 = B, SW66 = B, SW64 = B, SW63 = B, SW60 to 61 = B, SW53 = B, SW44 = ON, SW40 = B, SW39 = A, SW37 = A, SW24 to 26 = A, SW21 = A, SW18~19 = A, SW77 = OFF, SW74 = ON
Pin Name YS2 YS3 R S/H G S/H B S/H ANALOG OSD R IN ANALOG OSD G IN ANALOG OSD B IN ANALOG R IN ANALOG G IN ANALOG B IN H CURVE CORRECTION HVCO AFC FILTER CP IN HD IN VD IN SYNC IN VSM FILTER COLOR LIMITER Cr/Pr2 IN Cb/Pb2 IN Y2 IN LIGHT AREA DET FILTER Cr/Pr1 IN Cb/Pb1 IN Y1 IN BPH FILTER DARK AREA DET FILTER APL FILTER VSM OUT ABCL IN YM YS1 Symbol V1 V2 V4 V6 V7 V18 V19 V21 V24 V25 V26 V40 V42 V44 V49 V50 V52 V53 V57 V58 V60 V61 V63 V64 V66 V67 V68 V70 V71 V74 V77 V78 V79 V80 Test Circuit Min 4.2 4.2 4.2 3.65 3.65 3.65 3.65 3.65 3.65 2.2 4.4 5.4 1.8 7.5 6.65 4.7 4.7 4.7 4.7 4.7 4.7 5.5 4.8 4.1 6.1 Typ. 0.1 0.1 5.2 5.2 5.2 3.95 3.95 3.95 3.95 3.95 3.95 2.5 5.0 6.2 0 0 0 2.1 7.7 6.9 5.0 5.0 5.0 0.09 5.0 5.0 5.0 5.8 0.09 5.0 4.3 6.35 0.1 0.1 Max 0.2 0.2 6.2 6.2 6.2 4.25 4.25 4.25 4.25 4.25 4.25 2.8 5.6 7.0 0.3 0.3 0.3 2.4 7.9 7.15 5.3 5.3 5.3 0.15 5.3 5.3 5.3 6.1 0.15 5.2 4.5 6.6 0.2 0.2 V Unit
Pin No. 1 2 4 6 7 18 19 21 24 25 26 40 42 44 49 50 52 53 57 58 60 61 63 64 66 67 68 70 71 74 77 78 79 80

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Picture Quality (Sharpness) Block
Characteristics Y input dynamic range Black detection level shift Black stretch amp maximum gain Black stretch start point 1 Symbol DRY VB VB3 GBS PBST1 PBST2 Black stretch start point 2 PBS1 PBS2 PBSC1 PBSC2 Black stretch characteristic switch PBSC3 PBSC4 PBSC5 PBSC6 Black stretch area reinforcement current IBSA DV01 D.ABL detection voltage DV10 DV11 D.ABL sensitivity Black level correction Dark area Y correction point Dark area dynamic Y gain Dark area static Y gain Light area Y correction point Light area dynamic Y gain Light area static Y gain SDAMIN SDAMAX BLC PDGP GDDGMAX GDSGMIN GDSGMAX LPG GLDG GLSGMIN GLSGMAX DAMIN Dark area detection sensitivity DACEN DAMAX ADT100 DC restoration rate ADT135 ADT65 DC restoration point VDT0 VDT1 PDTL60 DC restoration limit PDTL75 PDTL87 PDTL100 Test Circuit (Note P19) 74 74 80 80 82 82 (Note P18) (Note P17) (Note P16) (Note P08) (Note P09) (Note P10) (Note P11) (Note P12) (Note P13) (Note P14) (Note P15) 1.4 0.25 0.88 0.95 0.9 1.2 0.55 -5 47 64 74 1.7 0.3 0.98 1.05 1.1 1.35 0.70 0 49 67 77 2.3 0.37 1.08 1.15 1.2 1.5 0.85 5 % 55 70 80 % times V (Note P07) (Note P06) (Note P05) Test Condition (Note P01) (Note P02) (Note P03) 50 0 (Note P04) 14 26 -8 26 -5.5 26 -3.5 13 80 240 380 0.25 4.5 25 5.5 -6.5 2 64 1.1 0.3 21 28 -6 28 -3 28 -2 18 120 280 420 0.01 0.28 6.5 28 6 -5 2.4 74 1.7 0.6 30 30 -4 30 -1 30 -0.5 23 160 320 460 0.02 V/V 0.31 8.5 33 6.5 -4 2.6 80 2.3 0.9 dB IRE dB IRE IRE dB dB mV A IRE 55 5 60 10 IRE Min 0.7 -15 35 2.4 20 Typ. 1.0 10 45 2.8 25 Max 1.5 15 mV 55 3.2 35 IRE dB Unit Vp-p
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Characteristics Symbol FAP00 Sharpness control peak frequency FAP01 FAP10 FAP11 DC fluctuation at switching sharpness control peak frequency VRDC GMAX00 GMIN00 GMAX01 Sharpness control range GMIN01 GMAX10 GMIN10 GMAX11 GMIN11 GCEN00 Sharpness control center characteristic GCEN01 GCEN10 GCEN11 TSRT00 2T pulse response SRT control TSRT01 TSRT10 TSRT11 VSM peak frequency FVSM GV000 GV001 GV010 VSM gain GV011 GV100 GV101 GV110 GV111 VSR1 VSM mute threshold voltage VSR2 VSR580 VSM limit Y input to R output delay time VLU VLD TYR YDLA Y delay time switch YDLB YDLC GAMIN Y group delay correction GBMIN GAMAX GBMAX Test Circuit (Note P27) 1 -5 1.7 -4 2.4 -2 (Note P26) (Note P25) 0.55 110 3 7 10 -4 2.5 0.66 125 5 10 15 -2.5 3 0.75 140 10 15 25 -1 3.5 dB ns ns Pins 1, 2, 80 (Note P24) 8.9 11.4 13.5 14.8 0.62 0.62 0.62 0.55 10.5 12.6 14.4 15.7 0.78 0.78 0.78 0.66 12.1 13.8 15.3 16.6 0.85 0.85 0.85 0.75 Vp-p V (Note P23) 6.7 11.5 19 -2 3.7 7.1 8.5 12.5 19.5 -40 -1.2 4.6 8.2 11.3 15.5 25.5 -35 -0.4 5.5 9.3 dB MHz (Note P22) 7 7 0.9 3.5 10 10 1.6 4.8 13 13 2.7 7.1 dB (Note P21) (Note P20) Test Condition Min 10.5 7 5 3.5 15 -4 15 -5 15 -7 15 -12 7 7 Typ. 13.5 9.5 7.2 4.5 0.01 17.5 -0.6 17.5 -0.3 17.5 -2.5 17.5 -5 10 10 Max 17 12 MHz 7.8 6.3 0.02 19 2.5 19 2.5 dB 19 1.5 19 0 13 13 dB V Unit
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Characteristics Symbol GCDE00 Color detail enhancer GCDE01 GCDE10 GCDE11 Y detail frequency FYD GYDMAX Y detail control range GYDCEN GYDMIN Test Circuit (Note P29) (Note P28) Test Condition Min 9 9 9 9 4 11 8 3 Typ. 10 10 10 10 5 13 10 5 Max 11 11 11 11 6 15 12 7 dB MHz dB Unit
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Color Difference Block 1: YUV input and matrix
Characteristics Color difference input dynamic range Symbol DRB DRR TRMAX Color difference tint control characteristic TRMIN TBMAX TBMIN FB00 Color SRT peak frequency FB01 FR00 FR01 GSB00CEN GSB00MAX GSB01CEN Color SRT gain GSB01MAX GSR00CEN GSR00MAX GSR01CEN GSR01MAX Cb1 input to B output delay time Cr1 input to R output delay time TB TR GCBDY1 Dynamic Y/C compensation GCBDY2 GCRDY1 GCRDY2 GY00 GY01 GCBB YUV gain GPBB GPBR GCRR GPRB GPRR Test Circuit (Note S03) (Note S02) (Note S01) 3.4 5.4 3.1 5.2 130 130 1.8 -1.65 1.8 -1.65 2.4 2.4 9.5 9.9 -18.0 9.5 -15.0 10.0 4.7 6.7 4.4 6.5 155 155 2.25 -1.2 2.25 -1.2 3.4 3.4 11.0 11.4 -16.0 11.0 -13.5 11.5 6.0 7.0 5.7 7.8 185 185 2.7 -0.75 2.7 -0.75 4.4 4.4 12.5 12.9 -14.0 12.5 -12.0 13.0 dB dB ns ns Test Condition Min 0.7 0.7 25 -37 27 -36 3.6 4.6 3.6 4.6 1.5 2.9 2.0 3.5 Typ. 0.9 0.9 29 -33 31 -32 4.5 5.8 4.5 5.8 2.8 4.2 3.3 4.8 Max 1.0 1.0 33 -29 35 -28 5.4 7.0 MHz 5.4 7.0 4.1 5.5 4.6 6.1 dB Unit Vp-p
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Characteristics Symbol GrA01 GrA10 GrA11 GrB01 GrB10 GrB11 GrC01 Green stretch GrC10 GrC11 GrD01 GrD10 GrD11 GrE01 GrE10 GrE11 Test Circuit (Note S04) Test Condition Min 0.98 0.95 0.93 1.01 1.05 1.12 1.10 1.23 1.35 1.09 1.21 1.32 0.98 0.95 0.93 Typ. 1 1 1 1.05 1.1 1.19 1.14 1.27 1.42 1.13 1.25 1.39 1 1 1 Max 1.02 1.05 1.07 1.10 1.15 1.26 1.18 1.31 1.49 1.17 1.29 1.46 1.02 1.05 1.07 times Unit
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Color Difference Block 2
Characteristics Color difference contrast adjustment characteristic Color adjustment characteristic Symbol VuCY vcCY+ vcCY- RMAX RCNT R-Y relative phase and amplitude RMIN VR/VBMAX VR/VBCNT VR/VBMIN GMAX GCNT G-Y relative phase and amplitude GMIN VG/vBMAX VG/vBCNT VG/vBMIN GHTRY Color difference halftone characteristic GHTGY GHTBY V1 Color characteristic V2 V3 Color limiter characteristic High-bright color gain CLT0 CLT1 HBC1 Test Circuit Test Condition (Note A01) Min 14.5 3.0 (Note A02) -35 109 98.5 88 0.86 0.65 0.42 251 244 229 0.43 0.33 0.22 0.47 (Note A03) 0.47 0.47 0.09 0.26 (Note A04) 0.44 0.60 1.45 (Note A05) 1.80 (Note A06) 0.02 2.00 0.04 2.20 0.06 times 0.58 0.70 1.65 0.72 0.80 1.85 Vp-p Typ. 16.0 4.0 -22 111.5 101 90 0.90 0.69 0.45 254 247 232 0.48 0.37 0.25 0.50 0.50 0.50 0.23 0.40 Max 17.5 5.0 -17 114 103.5 92 0.94 0.73 0.49 257 250 235 0.53 0.41 0.28 0.53 0.53 0.53 0.37 0.54 Vp-p times times times dB Unit dB

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Text Block
Characteristics Symbol GR AC gain (Y1in~R/G/B out) GG GB AC gain axis difference GG/R GB/R GfR Frequency characteristic (Y1in~R/G/B out) GfG GfB Frequency characteristic (Cb1/Cr1in~R/G/B out) Unicolor adjustment characteristic GfCb GfCr Vu VbrMAX Brightness adjustment characteristic VbrCNT VbrMIN White peak slice level Black peak slice level Vwps1 Vwps2 Vbps N12 RGB output S/N N13 N14 Halftone characteristic Halftone on voltage GHT1 GHT2 VHT VVR V-BLK pulse output level VVG VVB VHR H-BLK pulse output level VHG VHB BLK pulse delay time tdON tdOFF Sub-contrast variable range vsu+ vsu- CUT+ Cut-off voltage variable range CUT- V#12 RGB output voltage V#13 V#14 RGB output voltage 3-axis difference VOUT Test Circuit Test Condition Min 3.08 (Note T01) 3.08 3.08 0.94 0.94 30 At -3dB, sharpness characteristic is flat 30 30 (Note T02) 10 10 15.0 4.10 (Note T03) 3.05 1.95 2.20 (Note T04) 2.59 (Note T05) 1.15 (Note T06) 0.45 (Note T07) 0.45 Pin 79 0.65 0.30 0.50 0.85 0.80 0.80 0.80 0.80 0.80 0.80 0.00 0.08 2.45 -3.3 0.47 0.47 2.30 2.30 2.30 0 0.55 1.05 1.30 1.30 1.30 1.30 1.30 1.30 0.30 0.30 2.95 -2.8 0.52 V 0.42 2.05 2.05 2.05 0.52 2.55 2.55 2.55 150 mV V dB s V V V 2.74 1.35 -52 -52 -52 0.50 2.89 1.45 -46 -46 -46 0.55 times dB V Typ. 3.45 3.45 3.45 1.00 1.00 60 60 60 12.5 12.5 16.0 4.45 3.40 2.30 2.32 Max 3.90 3.90 3.90 1.06 1.06 17.0 4.80 3.75 2.65 2.44 Vp-p V MHz dB MHz times Unit

0.30 0.30 0.30
0.30 0.30 (Note T08) 1.95 -3.8 0.42

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Characteristics Symbol DRR1+ DRR1- DRR2+ DRR2- DRG1+ DRG1- DRG2+ Drive adjustment variable range DRG2- DRG3+ DRG3- DRB1+ DRB1- DRB2+ DRB2- DRB3+ DRB3- MURD Output voltage at P-mute MUGD MUBD P-mute ON voltage VMUTE BBR Output voltage at blue background BBG BBB Input impedance of #78 ACL characteristic Zin ACL1 ACL2 ABLP1 ABLP2 ABLP3 ABL point ABLP4 ABLP5 ABLP6 ABLP7 ABLP8 ABLG1 ABLG2 ABLG3 ABL gain ABLG4 ABLG5 ABLG6 ABLG7 ABLG8 Test Circuit Test Condition Min 2.5 -5.5 2.5 -5.5 2.5 -5.5 2.5 (Note T09) -5.5 2.5 -5.5 2.5 -5.5 2.5 -5.5 2.5 -5.5 1.7 Typ. 3.0 -5.0 3.0 -5.0 3.0 -5.0 3.0 -5.0 3.0 -5.0 3.0 -5.0 3.0 -5.0 3.0 -5.0 1.85 1.85 1.85 2.15 1.2 1.2 1.25 30 -4.5 -13.5 -0.16 -0.23 -0.32 -0.40 -0.49 -0.57 -0.65 -0.70 -0.02 -0.12 -0.29 -0.47 -0.63 -0.80 -0.96 -1.04 Max 3.5 -4.5 3.5 -4.5 3.5 -4.5 3.5 -4.5 3.5 -4.5 3.5 -4.5 3.5 -4.5 3.5 -4.5 2.0 2.0 2.0 2.40 1.4 V 1.0 1.1 (Note T10) (Note T11) 24 -6.5 -15.0 -0.21 -0.28 -0.37 (Note T12) -0.45 -0.54 -0.62 -0.70 -0.75 -0.06 -0.17 -0.34 (Note T13) -0.52 -0.68 -0.85 -1.01 -1.09 1.4 1.4 36 -2.5 -11.0 -0.11 -0.18 -0.27 -0.35 -0.44 -0.52 -0.60 -0.65 0.00 -0.07 -0.24 -0.42 -0.59 -0.75 -0.91 -0.99 V V Vp-p k dB V V dB Unit

Pin 79
1.7 1.7 1.90 1.0
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Characteristics Symbol V12R V13R V14R V12G RGB output mode V13G V14G V12B V13B V14B 1 2 Y-OUT characteristic 1 2 3 BSPmin BSPcnt White-peak blue characteristic BSPmax BSGmin BSGcnt BSGmax Forced BLK input threshold voltage VBLKIN ACBR ACBG ACBB VACB1R VACB1G ACB insertion pulse phase and amplitude VACB1B VACB2R VACB2G VACB2B VACB3R VACB3G VACB3B IKR IK input amplitude IKG IKB IK input cover range DIKin+ DIKin- Test Circuit Test Condition Min 2.15 0.30 0.30 0.30 (Note T14) 2.15 0.30 0.30 0.30 2.15 56 72 (Note T15) 0.49 -1.67 -4.59 37 72 101 (Note T16) 2.1 6.4 9 Pin 79 5.1 0.15 0.15 0.15 (Note T17) 0.27 0.27 0.27 0.52 0.52 0.52 0.73 (Note T18) 0.73 0.73 3.00 (Note T19) -0.50 0.32 0.32 0.32 0.57 0.57 0.57 0.93 0.93 0.93 3.30 -0.30 0.37 0.37 0.37 0.62 0.62 0.62 1.13 1.13 1.13 3.60 -0.10 V Vp-p Vp-p 3.1 7.4 10 5.6 1 2 3 0.20 0.20 0.20 4.1 8.4 11 6.1 0.25 0.25 0.25 H V dB Typ. 2.40 0.80 0.80 0.80 2.40 0.80 0.80 0.80 2.40 66 82 1.24 -0.92 -3.84 42 77 106 Max 2.65 1.30 1.30 1.30 2.65 1.30 1.30 1.30 2.65 76 IRE 92 1.99 -0.17 -3.09 47 82 111 IRE dB V Unit

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Characteristics Symbol GTXR Analog RGB gain GTXG GTXB Analog RGB gain 3-axis difference GTXG/R GTXB/R GfTXR Analog RGB frequency characteristic GfTXG GfTXB DR24 Analog RGB input dynamic range DR25 DR26 TXVWPSR Analog RGB white peak slice level TXVWPSG TXVWPSB VBPSR Analog RGB black peak limit level VBPSG VBPSB vuTXR RGB contrast adjustment characteristic vuTXG vuTXB VbrTXmax Analog RGB bright adjustment characteristic Analog RGB mode switching voltage VbrTXcnt VbrTXmin VTXON RYS tPRYS Analog RGB mode switching transfer characteristic tRYS FYS tPRYS tRYS Text ACL characteristic TXACL1 TXACL2 GOSDR Analog OSD gain GOSDG GOSDB Analog OSD gain 3-axis difference GOSDG/R GOSDB/R GfOSDR Analog OSD frequency characteristic GfOSDG GfOSDB DR18 Analog OSD input dynamic range DR19 DR21 Test Circuit Test Condition Min 3.03 (Note T20) 3.03 3.03 0.94 0.94 30 At -3dB 30 30 0.80 0.80 0.80 2.45 (Note T21) 2.45 2.45 1.15 (Note T22) 1.15 1.15 15.5 (Note T23) 15.5 15.5 3.0 (Note T24) 2.6 2.1 Pin 2 0.65 (Note T25) (Note T26) -6.7 -16.5 2.95 (Note T27) 2.95 2.95 0.94 0.94 35 At -3dB 35 35 0.80 0.80 0.80 Typ. 3.40 3.40 3.40 1.00 1.00 35 35 35 1.20 1.20 1.20 2.70 2.70 2.70 1.30 1.30 1.30 16.5 16.5 16.5 3.2 2.8 2.3 0.85 15 20 0 10 30 0 -4.7 -14.5 3.30 3.30 3.30 1.00 1.00 40 40 40 1.20 1.20 1.20 Max 3.83 3.83 3.83 1.06 1.06 1.50 1.50 1.50 2.95 2.95 2.95 1.45 1.45 1.45 18.5 18.5 18.5 3.4 3.0 2.5 1.05 50 50 10 ns 50 50 10 -2.7 -12.5 3.70 3.70 3.70 1.06 1.06 1.50 1.50 1.50 Vp-p MHz times dB V V dB V Vp-p Vp-p MHz times Unit

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Characteristics Symbol OSDVWPSR Analog OSD input white peak slice level OSDVWPSG OSDVWPSB OSDVBPSR Analog OSD black peak limit level OSDVBPSG OSDVBPSB VUOSDR11 VUOSDG11 VUOSDB11 VUOSDR10 VUOSDG10 OSD contrast adjustment characteristic VUOSDB10 VUOSDR01 VUOSDG01 VUOSDB01 VUOSDR00 VUOSDG00 VUOSDB00 VbrOSD0 Analog OSD bright adjustment characteristic VbrOSD1 VbrOSD2 VbrOSD3 Analog OSD mode switching voltage VOSDON1 VOSDON2 RYS1 tPRYS1 tPRYS1 FYS1 tPRYS1 Analog OSD mode switching transfer characteristic tPRYS1 RYS2 tPRYS2 tPRYS2 FYS2 tPRYS2 tPRYS2 OSDACL1 OSD ACL characteristic OSDACL2 OSDACL3 OSDACL4 Test Circuit Test Condition Min 2.45 (Note T28) 2.45 2.45 1.30 (Note T29) 1.30 1.30 0.58 0.58 0.58 0.47 0.47 0.47 (Note T30) 0.31 0.31 0.31 0.19 0.19 0.19 2.20 2.05 (Note T31) 1.95 1.80 Pin 80 Pin 1 2.05 2.05 2.15 2.00 2.30 2.30 15 20 0 10 30 0 15 20 0 10 30 0 0.00 0.00 -4.7 -14.5 2.35 2.20 2.55 V 2.55 50 50 10 50 50 10 ns 50 50 10 50 50 10 0.37 0.37 0.37 0.22 0.22 0.22 2.40 2.25 0.45 0.45 0.45 0.24 0.24 0.24 2.60 2.45 V Typ. 2.70 2.70 2.70 1.45 1.45 1.45 0.64 0.64 0.64 0.53 0.53 0.53 Max 2.95 2.95 2.95 1.60 1.60 1.60 0.71 0.71 0.71 0.59 0.59 0.59 Vp-p V Vp-p Unit

(Note T33) (Note T32)

-6.7 -16.5

-2.7 -12.5 dB
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Characteristics Symbol 41TV1 42TV1 43TV1 41TV2 42TV2 43TV2 41TV3 42TV3 OSD blending characteristic 43TV3 41OSD1 42OSD1 43OSD1 41OSD2 42OSD2 43OSD2 41OSD3 42OSD3 43OSD3 Y RGB input Y OSD input RGB input Y RGB input OSD input Input crosstalk OSD input Y OSD input RGB input RGB input in three axes OSD input in three axes VV A VV O VA V VA O VO V VO A BLPmin Blue stretch point/gain BLPmax BLGmin BLGmax BL1 Blue stretch correction BL2 BL3 BL4 WPL1 White letters improvement WPL2 WPL3 Test Circuit Test Condition Min -7 -7 -7 -4 -4 -4 Typ. -6 -6 -6 -3 -3 -3 -55 -55 -55 -5.5 -5.5 -5.5 -10.5 -10.5 -10.5 -40 -40 -40 -50 -55 -50 -50 -45 -50 -50 -50 28 60 2.9 6.4 89 94 98 103 21 56 102 Max -5 -5 -5 -2 -2 -2 -50 -50 -50 -4.5 -4.5 -4.5 -9.0 -9.0 -9.0 -30 -30 -30 -45 -45 -45 -45 -40 -45 -40 -40 33 IRE 55 (Note T35) 2.4 5.4 84 89 (Note T36) 93 98 16 (Note T37) 51 97 103 108 25 61 107 Vp-p 3.4 dB 7.4 94 99 IRE 65 dB dB Unit

Input: Signal 1 (fo = 1 MHz, Amplitude 0.7 Vp-p) Input: Signal 1 (fo = 4 MHz, Amplitude 0.7 Vp-p) (Note T34)

-6.5 -6.5 -6.5 -12.0 -12.0 -12.0

23
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TA1360AFG
Sync Block
Characteristics Sync input horizontal sync phase HD input horizontal sync phase Symbol SPH HDPH HDDUTY1 Polarity detecting rage HDDUTY2 HDDUTY3 HDDUTY4 VthS00 Sync input threshold amplitude VthS01 VthS10 VthS11 HD input threshold voltage Horizontal picture position (phase) adjustment variable range Horizontal picture position (phase) shift switching amount Curve correction variable amount VthHD HSFT- HSFT+ HSFT H#40 CPS0 CPW0 CPV0 CPS1 Clamp pulse phase/width/level CPW1 CPV1 CPS2 CPW2 CPV2 HBPS00a HBPS00b HBPS01a Black peak detection pulse phase HBPS01b HBPs10a HBPs10b HBPs11a HBPs11b FBP threshold HVCO oscillation start voltage H-OUT start voltage H-OUT stop voltage H-OUT pulse duty VthFBP VVCO VHON VHOFF THA THB Test Circuit (Note HA03) Test Condition (Note HA01) (Note HA02) Min 0.55 0.58 62 47.5 10 18 (Note HA04) 26 34 (Note HA05) (Note HA06) 11 (Note HA07) 5.2 2.9 3.1 2.0 4.7 0 (Note HA08) 1.9 4.7 3.2 2.2 4.7 1.2 1.2 6.0 6.0 (Note HA09) 10.0 10.0 16.0 16.0 (Note HA10) Pin 42: Monitor, VCC voltage Pin 37: Monitor, VCC voltage Pin 37: Monitor, VCC voltage (Note HB01) 44 47 49 4.8 3.0 5.0 4.3 38 13.0 13.0 18.0 18.0 5.3 4.0 6.0 5.3 41 15.0 15.0 21.0 21.0 5.8 5.0 7.0 6.3 43 % V V V V 12.5 6.7 3.4 3.8 2.5 5.0 0.7 2.4 5.0 4.2 2.7 5.0 3.0 3.0 8.0 8.0 14 9.2 3.9 4.5 % 3.0 5.3 1.5 % 2.9 5.3 5.2 % 3.2 5.3 5.9 5.9 11.0 11.0 % V V V % % 0.65 11 32 40 0.75 12.5 38 46 0.85 14 % Vp-p Typ. 0.65 0.68 0.5 67 99.5 52.5 16 24 Max 0.75 0.78 2.0 72 % 98 57.5 22 30 % Unit s s

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Characteristics Symbol F15K F28K Horizontal free-run frequency F31K F33K F37K F45K F15KMIN F15KMAX F28KMIN F28KMAX F31KMIN Horizontal oscillation frequency variable range F31KMAX F33KMIN F33KMAX F37KMIN F37KMAX F45KMIN F45KMAX BH15K BH28K Horizontal oscillation control sensitivity BH31K BH33K BH37K BH45K H-OUT output voltage Pin 55 Horizontal oscillation frequency control voltage threshold VHOH VHOL VfHSW1 VfHSW2L Pin 41 VfHSW2M VfHSW2H DAC1 DAC switch voltage DAC2 VP output pulse width 000 001 010 Vertical free-run (maximum pull-in range) 011 100 101 110 Vertical minimum pull-in range VDAC1H VDAC1L VDAC2H VDAC2L VPW VPt0 VPt1 VPt2 VPt3 VPt4 VPt5 VPt6 TVPULL Test Circuit Test Condition Min 15.59 27.90 (Note HB02) 31.19 33.41 37.60 44.52 14.78 16.37 26.00 28.90 29.47 32.72 (Note HB03) 31.41 34.91 36.50 40.20 43.20 47.85 176 320 352 Hz/0.1 V (Note HB04) 376 390 520 4.8 (Note HB05) 1.7 1.3 4.3 7.3 TEST = (00), DAC1 = (0) TEST = (00), DAC1 = (1) TEST = (00), DAC2 = (1) TEST = (00), DAC2 = (0) (Note V01) 8.5 8.5 4 1278 846 722 657 610 360 304 (Note V02) 47 470 480 650 5.1 0.1 2.0 1.5 4.5 7.5 9.0 0.3 9.0 0.3 4.5 1281 849 725 660 613 363 307 48 564 570 780 5.2 V 0.3 2.3 1.7 V 4.7 7.7 0.7 0.7 5 1284 852 728 663 616 366 310 49 H H H V 31.94 35.62 37.30 41.10 44.00 48.65 220 400 440 32.57 36.33 38.20 42.10 44.80 49.45 264 480 528 Typ. 15.75 28.125 31.5 33.75 37.9 45.0 15.08 16.70 26.90 29.70 30.06 33.39 Max 15.91 28.35 31.82 34.09 38.40 45.48 15.38 17.03 27.80 30.60 30.65 34.06 kHz kHz Unit

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Characteristics 000 Symbol VBPP0E VBPP0S 001 VBPP1E VBPP1S 010 Vertical black peak detection pulse VBPP2E VBPP2S 011 VBPP3E VBPP3S 100 VBPP4E VBPP4S 101 VBPP5E VBPP5S 110 VBPP6E VBPP6S Vertical blanking end phase High VP output voltage Low VBLKMIN VBLKMAX VVPH VVPL 15.75 kHz 28.125 kHz 31.5 kHz SYNC input to VP output delay time 33.75 kHz 37.9 kHz 45 kHz 000 CBLK1000min CBLK1000max 001 CBLK1001min CBLK1001max 010 Compression BLK 1 (start phase) CBLK1010min CBLK1010max 011 CBLK1011min CBLK1011max 100 CBLK1100min CBLK1100max 101 CBLK1101min CBLK1101max 110 CBLK1110min CBLK1110max Test Circuit Test Condition Min 51 Typ. 52 Max 53 Unit

pin 35 voltage (Note V04) (Note V03)
1099.5 1100.5 1101.5 51 729.5 49.5 599.5 49.5 544.5 51 499.5 51 289.5 51 239.5 15 45 4.6 10.0 5.4 4.8 4.4 3.9 3.1 1087 1117 719 749 591 621 527 557 487 517 279 309 223 253 52 730.5 50.5 600.5 50.5 545.5 52 500.5 52 290.5 52 240.5 16 46 5.0 0.1 11.6 6.4 5.8 5.4 4.8 4.1 1088 1118 720 750 592 622 528 558 488 518 280 310 224 254 53 731.5 51.5 601.5 51.5 546.5 53 501.5 53 291.5 53 241.5 17 H 47 5.4 V 0.5 13.4 8.8 7.6 7.2 6.6 5.9 1089 1119 721 751 593 623 529 H 559 489 519 281 311 225 255 s H
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Characteristics 000 Symbol CBLK2000min CBLK2000max 001 CBLK2001min CBLK2001max 010 Compression BLK 2 (end phase) CBLK2010min CBLK2010max 011 CBLK2011min CBLK2011max 100 CBLK2100min CBLK2100max 101 CBLK2101min CBLK2101max 110 External V-BLK input current CBLK2110min CBLK2110max IEXTBLK Test Circuit Test Condition Min 49 77 49 77 49 77 49 77 49 77 49 77 49 77 Pin 35 input current 520 Typ. 50 78 50 78 50 78 50 78 50 78 50 78 50 78 625 Max 51 79 51 79 51 79 51 79 51 79 51 79 51 79 780 A H Unit

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Test Condition for Picture Quality (Sharpness) Block
Common Test Condition for Picture Quality (Sharpness) Block
1. 2. 3. 4. SW67 = SW66 = B, SW63 = B, SW60 to SW61 = B, SW44 = ON, SW40 = B, SW18 to SW26 = A, SW77 = OPEN Send bus control data as preset values, turn ACB operation switching to ACB OFF (00), select Sync input (1), turn P-MODE to Normal 1(000), WPL-LEVEL to max (111), and change subaddress (1C) to (03). Input sync signal, which is in sync with input signal for testing except "Sweep", to #53 (Sync input). "H-Freq." should be the same frequency as the one of #53. Set Y/color difference input mode to (0), sync separator level to 20 % (01), and vertical free-running frequency to 307H (110).
Test Conditions SW Mode SW70 SW68 SW64 C C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. Connect external power supply PS to #68, and monitor #70 and #74. 2. 3. 4. 5. Set black stretch point 1 to OFF (000), and black detection level to 0 IRE (1). Increase PS voltage from 4.95 V in steps of 1 mV. At the moment when #70 picture period (High) drops to Low level, monitor DC difference on #74 VB. Set black detection level to 3 IRE (0). Repeat the step 3 above and monitor DC difference, VB3 on #74.
Note No. P01
Characteristics SW71 Black detection level shift B
#74 waveform VB, VB3
#70 waveform
P02
Black stretch amp maximum gain
B
A
A
B
OPEN
1. 2. 3. 4. 5.
Set SW70 to A (maximum gain), and input 500-kHz sine wave to TPA. Adjust signal amplitude to 0.1 Vp-p on #68. Set black stretch point 1 to OFF (000), and measure #74 amplitude VA. Set black stretch point 1 to 001 (black stretch ON), and measure #74 amplitude VB. Calculate GBS using a following equation. GBS = 20 x log (VB / VA) [dB]
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Note No. P03 Characteristics SW71 Black stretch start point 1 A Test Conditions SW Mode SW70 SW68 SW64 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. 4. 5. Set SW70 to A (maximum gain), and black stretch point 1 to OFF (000). Apply 0 V to #71. Connect external power supply PS to #68, increase voltage from V3, and plot #74 voltage change S1. The #74 voltage is set as V0 when V3 is applied, and as V100 when V3 + 0.7 V is applied. Set black stretch point 1 to minimum (001), increase PS voltage from V3, and then plot #74 voltage change S2. Set black stretch point to maximum (111), repeat 3 above, then plot #74 voltage change S3. Determine intersection points of S1, S2 (VBST1), and S3 (VBST2) as shown in the figure below. Also calculate PBST1 and PBST2 using following equations. VZ [V] = V100 [V] - V0 [V] PBST1 [(IRE)] = [(VBST1 [V] - V74 [V]) / VZ] x 100 (IRE) PBST2 [(IRE)] = [(VBST2 [V] - V74 [V]) / VZ] x 100 (IRE)
#74
S3 VBST2
S1
VBST1 S2
V74 #68
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TA1360AFG
Note No. P04 Characteristics SW71 Black stretch start point 2 A Test Conditions SW Mode SW70 SW68 SW64 A A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. Set black stretch point 1 to OFF (000), apply 0 V to #71, input TG7 LINEARITY to TPA, adjust amplitude on #68 as shown in the figure below, set unicolor to center (1000000), and measure amplitude of #12 (R OUT), VP12. Set black stretch point 1 to 001 (black stretch ON), connect external power supply PS to #74, and monitor #12 (R OUT). Set black stretch start point 2 data to minimum (00). When PS is V74 (APL 0%), and V74 + 1.0 V (APL 100%), determine black stretch start point difference V00 as shown in the figure below. (Monitor input waveform and output waveform with an oscilloscope, adjust the both waveforms to have the same amplitude (gradient), and compare them to determine the bend point of the output.) Set black stretchstart point 2 data to maximum (11), determine black stretch start point difference V11. Calculate following equations. PBS1 = (V00/VP12) x 100 PBS2 = (V11/VP12) x 100 LINEARITY
2. 3.
4. 5.
APL 100% 0.7 Vp-p APL 0%
V***
0.3 Vp-p #68 waveform (linearity) #12 (R OUT)
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Note No. P05 Characteristics SW71 Black stretch characteristic switch A Test Conditions SW Mode SW70 SW68 SW64 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. 4. Set SW70 to A (maximum gain), black stretch point 1 (18) to maximum (E0), subaddress (1C) data to (00) and (1E) data to (08). Apply 0 V to #71 and connect external power supply PS to #68. Set PS to V68 + 0.7 V, and adjust unicolor so that DC level of #12 is +1.0 V. Plot voltage change S4 of #12 (voltage in picture period). Determine intersection points (VBSC1 and VBSC2) of S2 and S4 obtained from the plot in black stretch start point 1. Then calculate PBSC1 and PBSC2 using following equation. Set black stretch characteristic switch subaddress data (1C)/(1E) to (20)/(00) and (20)/(08) respectively. As described in steps 2 and 3, determine intersection points (VBSC3, VBSC4, VBSC5 and VBSC6) and calculate PBSC3, PBSC4, PBSC5 and PBSC6. PBSC* = (VBSC* [V] - V12 [V]) / 1.0 x 100 [(IRE)]
#12
VBSC2 V12 V68
S2 #68
V68 + 0.7 V
VBSC1 S4 Black stretch characteristic switch ON
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Note No. P06 Characteristics SW71 Black stretch area reinforcement current B Test Conditions SW Mode SW70 SW68 SW64 C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. Connect external power supply PS1 to #68. 2. Leave SW70 open, put an ammeter between SW70A and #70, connect external power supply PS2 to SW70A, set PS1 to 5.7 V, and set PS2 to 5 V. 3. Measure current value IBSA0 and IBSA1 when bus data of black stretch area reinforcement [18] is set to ON [80] and OFF [81]. Calculate IBSA using the following equation. IBSA = IBSA0 IBSA1
SW70 A mmeter PS2 5V
P07
D.ABL detection voltage
B
A
C
B
OPEN
1. 2. 3. 4.
Set D.ABL sensitivity to maximum (11), and black stretch point 1 to OFF (000). Connect external power supply PS to #78 and decrease voltage from 6.5 V. Repeat 2 when D.ABL detection voltage is changed to 00, 01, 10, and 11. At the moment when #74 picture period changes to Low, measure respective PS voltages V00, V01, V10, and V11. Calculate voltage differences between V00 and V01 (DV01), between V00 and V10 (DV10), and between V00 and V11 (DV11) DV*** = V00 - V01 (V10, V11) #74 undetected
#74 detected
#70 waveform
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Note No. P08 Characteristics SW71 D.ABL sensitivity B Test Conditions SW Mode SW70 SW68 SW64 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. Set black stretch point 1 to OFF (000), and connect external power supply to #78. Set D.ABL detection voltage to minimum (00). Interrelation between #78 voltage and #74 voltage when D.ABL sensitivity is set to minimum (00) and maximum (11) can be plotted as figure shown below. Measure gradients SDAMIN and SDAMAX using the figure below. SDAMIN = Y/X SDAMAX = Y/X
#74
10%
100%
Y
10%
X
#78
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Note No. P09 Characteristics SW71 Black level correction B Test Conditions SW Mode SW70 SW68 SW64 A A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. Set black stretch point 1[18] to OFF (00). Input signal of 0.7-V picture period amplitude to #68, and measure #12 picture period amplitude VB [V]. Set black level correction [18] to ON [04], determine DC change VBLC [V], and calculate BLC [V] using the following equation BLC = (VBLC/VB)] x 100 [(IRE)] #12 VBLC VB Black level correction OFF Black level correction ON
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Note No. P10 Characteristics SW71 Dynamic Y correction point A Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. 4. 5. 6. Connect external power supply PS1 to #68, PS2 to TP1, and set PS2 to 0 V. Set dark area dynamic Y gain VS dark area to MIN (00), static Y gain1 to OFF (000). Increase PS1 from V68 [V] to V68 [V] + 0.7 V and plot voltage change of #12 picture period. Take 0 for V68 [V] when the change is plotted. (V68 is pin voltage of pin 68) Set dark area dynamic Y gain VS dark area max (11), static Y gain1 to max (111) and PS2 to 1.2 V. Increase PS1 from V68 [V] to V68 [V] + 0.7 V and plot voltage change of #12 picture period. Measure VDGP by the following figure, and PDGP using the following equation. DGP = (VDGP [V] - V68 [V])/0.7 [V] x 100
#12 voltage [V]
ON OFF
V68
VDGP
#68 voltage [V] V68 + 0.7V (100 IRE)
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Note No. P11 Characteristics SW71 Dark area dynamic Y gain A Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. 4. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V. Set dark area dynamic Y gain [1C] to MIN [03], and dark area static Y gain [1C] to 0dB [17]. Set PS1 to V68 [V], and measure #12 picture period voltage VDDGV68 [V]. Set PS1 VDGP [V], and measure #12 picture period voltage VDDGMIN [V]. Set dark area dynamic Y gain [1C] to MAX [D7], PS2 to 1.2 V, measure voltage VDDGMAX [V] of #12 picture period when PS1 is VDGP [V], and calculate the following equations. VDDGMAX - VDDGMIN = A VDDGMIN - VDDGV68 = B GDDGMAX = 20 log [B/(B-A)] [dB] #12 voltage [V]
OFF VDDGMAX VDDGMIN VDDGV68 VDDGMIN - VDDGV68 = B #68 voltage [V] V68 + 0.7 V (100IRE) ON VDDGMAX - VDDGMIN = A
V68 VDGP
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TA1360AFG
Note No. P12 Characteristics SW71 Dark area static Y gain A Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area dynamic Y gain [1C] to MIN [03], and dark area static Y gain [1C] to OFF [03]. 3. Set PS1 to V68 [V], and measure #12 picture period voltage VSGOFF1 [V]. 4. Set PS1 to VDGP [V], and measure #12 picture period voltage VSGOFF2 [V]. 5. Set dark area static Y gain [1C] to MAX [1F], PS1 to VDGP [V], measure #12 picture period voltage VSGMAX, and calculate GDSGMAX using the following equations. VSGMAX - VSGOFF2 = A VSGOFF2 - VSGOFF1 = B GDSGMAX = 20 x log [B/(B - A)] [dB] #12 voltage [V]
OFF VSGMAX VSGOFF2 VSGOFF1 V68 VDGP #68 voltage [V] V68 + 0.7 V (100IRE) ON VSGMAX - VSOFF2 = A
6. Set dark area static Y gain [1C] to MIN [07], PS1 to VDGP [V], measure #12 picture period voltage VSGMIN, and calculate GDSGMIN using the following equation. GDSGMIN = 20 x log [(VSGMIN - VSGOFF1)/(VSGOFF2 - VSGOFF1)] [dB] #12 voltage [V]
OFF
VSGOFF2 VSGMIN VSGOFF1
ON V68 VDGP
VSGOFF2 - VSGOFF1 VSGMIN - VSGOFF1 #68 voltage [V] V68 + 0.7 V (100IRE)
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Note No. P13 Characteristics SW71 Light area Y correction point A Test Conditions SW Mode SW70 SW68 SW64 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area static Y gain [1C] to 0dB [17], and bright area static Y gain [1C] to 0dB [17]. 3. Increase PS1 from V68 [V] to V68 [V] + 0.7 [V], and plot the voltage change of #12 picture period. Take 0 for V68 [V] when the change is plotted. (V68 is pin voltage of pin 68) 4. Set light area static Y gain [1C] to MAX [04]. 5. Increase PS1 from V68 [V] to V68 [V] + 0.7 [V], and plot the voltage change of #12 picture period. 6. Measure VLGP using the following figure, and PLGP using the following equation. LGP = (VLGP [V] - V68 [V])/0.7 [V] x 100 (IRE) #12 voltage [V] ON
OFF
V68
VLGP
#68 voltage V68 + 0.7 V (100IRE)
54
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Note No. P14 Characteristics SW71 Light area dynamic Y gain A Test Conditions SW Mode SW70 SW68 SW64 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. 4. 5. Connect external power supply PS1 to #68, external power supply PS2 to TP7, and set PS2 to 1.2 V. Set dark area static Y gain [1C] to 0dB [17], and light area static Y gain [1C] to 0dB [17]. Set PS1 to V68 [V], and measure #12 picture period voltage VLDGOFF1. Set PS1 to VLGP [V], and measure #12 picture period voltage VLDGOFF2. Set light area static Y gain [1C] to MAX [14], PS2 to 0 V, PS1 to VLGP [V], determine #12 picture period voltage VLDGMAX [V] using the following equations. VLDGMAX - VLDGOFF2 = A VLDGOFF2 - VLDGOFF1 = B GLDG = 20 x log [B/(B - A)]
#12 voltage [V]
VLDGMAX VLDGOFF2 ON VLDGMAX - VLDGOFF2 = A VLDGOFF2 - VLDGOFF1 = B OFF VLDGOFF1 V68 VLGP V68 + 0.7 V (100IRE) #68 voltage
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Note No. P15 Characteristics SW71 Light area static Y gain B Test Conditions SW Mode SW70 SW68 SW64 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. 2. 3. 4. 5. Connect external power supply PS1 to #68, external power supply PS2 to TP7, and set PS2 to 0 V. Set dark area static Y gain [1C] to 0dB [17], and light area static Y gain [1C] to 0dB [17]. Set PS1 to V68 [V], and measure #12 picture period voltage VLSGOFF1 [V]. Set PS1 to VLGP [V], and measure #12 picture period voltage VLDGOFF2 [V]. Set light area static Y gain [1C] to MAX [14], PS1 to VLGP [V], measure #12 picture period voltage VlSGMAX, and calculate GLASGMAX [dB] using the following equations. VLSGMAX - VLSGOFF2 = A VLSGOFF2 - VLSGOFF1 = B GLSGMAX = 20 x log [B/(B - A)] [dB] #12 voltage [V]
VLSGMAX VLSGOFF2 ON VLSGMAX - VLDGOFF2 = A VLSGOFF2 - VLSGOFF1 = B OFF VLSGOFF1 V68 VLGP #68 voltage [V] V68 + 0.7 V (100IRE)
6.
Set light area static Y gain [1C] to MIN [16], PS1 to VLGP [V], measure #12 picture period voltage VLSGMIN, and calculate GLASGMIN [dB] using the following equations. VLSGMIN - VLSGOFF2 = C VLSGOFF2 - VLSGOFF1 = B GLSGMIN = 20 x log [B/(B - C)] [dB] #12 voltage [V]
VLSGMIN ON VLSGMIN - VLDGOFF2 = C VLSGOFF2 - VLSGOFF1 = B OFF VLSGOFF1 V68 VLGP #68 voltage [V] V68 + 0.7 V (100IRE)
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Note No. P16 Characteristics SW71 Dark area detection sensitivity A Test Conditions SW Mode SW70 SW68 SW64 B A A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 OPEN 1. Input the signal whose picture period amplitude is 0.18 V to #68 as shown in the figure below. 2. Measure #71 pin voltage DAMIN, DACEN, and DAMAX [V] when dark area detection sensitivity [1D] is set to MIN [00], CEN [04] and MAX [07].
#68 0.18 V
#71 DAMIN CEN MAX [V]
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Note No. P17 Characteristics SW71 DC restoration rate correction gain B Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. 5. 6. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80% (11), and connect external power supply PS1 to #68. Monitor DC level of #12 picture period. Set PS1 to V68 + 0.7 V, and adjust uncolor so that DC level is + 0.7. Set DC restoration correction rate to minimum (000), and measure VDT1 and VDT2 of V68 [V] and V68 + 0.1 V as shown in the figure below. Set #68 to V68 + 0.1 V, DC restoration correction rate to maximum (111), and measure VDT3. Set DC restoration correction rate SW to less than 100 % (1), #68 to V68 + 0.1 V, DC restoration correction rate to maximum (111), and measure VDT4. Calculate ADT100, ADT135, and ADT65 using following equations. ADT100 = (VDT2 [V] - VDT1 [V]) / 0.1 [V] ADT135 = (VDT3 [V] - VDT1 [V]) / 0.1 [V] ADT65 = 1 - ( (VDT2 [V] - VDT4 [V]) / 0.1 [V])
V68 [V]
Picture period
VDT1
V68 + 0.1 V
#12 waveform
VDT2 VDT3 VDT4
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Note No. P18 Characteristics SW71 DC restoration rate correction point B Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. 5. 6. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80% (11), and connect external power supply PS1 to #68. Monitor DC level of #12 picture period. Set PS1 to V68 + 0.7 V, and adjust unicolor so that DC level is + 1.0. Set DC restoration correction rate to minimum (000), and increase PS1 from V68. Plot relation between #74 (DC voltage) and #12 (voltage in picture period). Set DC restoration correction rate to maximum (111), and increase PS1 from V68. Plot relation between #74 and #12. Set DC restoration correction rate to maximum (111), DC restoration rate correction point (111), and increase PS1 from V68. Plot relation between #74 and #12. Determine VDT0, and VDT1 using the following equations. VDT0 = [(VSP0 - V74)/1 V] x 100% VDT1 = [(VSP1 - V74)/1 V] x 100%
#12
DC restoration rate correction point 000 DC restoration rate correction point 111
DC restoration correction rate 000 VSP0 VSP1
VPC
#74
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Note No. P19 Characteristics SW71 DC restoration rate correction limit point B Test Conditions SW Mode SW70 SW68 SW64 B B C Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. Set unicolor to maximum (1111111), DC restoration rate correction point to minimum (000), and connect external power supply PS1 to #74. Set DC restoration correction rate to maximum (111). Increase PS from 5 V. Monitor #12, and plot DC restoration correction amount. Repeat the step 3 above by changing data at DC restoration rate correction limit point. Measure the value using the figure below. Calculate PDTL60, PDTL75, PDTL87, and PDTL100 using following equations. PDTL60 = [(VL60 - V74)/1.0] x 100% PDTL75 = [(VL75 - V74)/1.0] x 100% PDTL87 = [(VL87 - V74)/1.0] x 100% PDTL100 = [(VL100 - V74)/1.0] x 100%
#12 100% (00)
87% (01)
73% (10)
60% (11)
VL60 VL75
VL100 VL87
#74
60
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Note No. P20 Characteristics SW71 DC fluctuation at switching sharpness control peak frequency B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. Set unicolor [05] to MAX [7F], SRT gain [19] to MIN [00], and CDE [15] to CEN [80]. Input setup signal (0.2 Vp-p) to TPA as shown in the figure below. Set sharpness [09] to MIN [00] and MAX [80]. Monitor #43, measure DC level VRDCMIN and VRDCMAX [V]. Calculate VRDC [V] using the following equation. VRDC = VRDCMIN - VRDCMAX [V] #68 0.2 V
#12 VRDC*
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Note No. P21 Characteristics SW71 Sharpness control range B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. 5. 6. 7. 8. 9. Input sine wave to TPA. (The frequency is variable.) Set #68 amplitude to 20 mVp-p. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M (00), and color detail enhancer (CDE) to center (10). Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #12. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V100. Set picture sharpness to maximum (1111111). Set input frequency to FAP00, measure the amplitude VMAX00, and calculate GMAX00 using the following equations. Set picture sharpness to minimum (0000000). Set input frequency to FAP00, measure the amplitude VMIN00, and calculate GMIN00 using the following equations. Set APACON peak frequency to 9.5 M (01). Set input frequency to FAP01, measure VMAX01/VMIN01 and calculate GMAX01/GMIN01. Set APACON peak frequency to 6.4 M (10). Set input frequency to FAP10, measure VMAX10/VMIN10 and calculate GMAX10/GMIN10.
10. Set APACON peak frequency to 4.5 M (11). Set input frequency to FAP11, measure VMAX11/VMIN11 and calculate GMAX11/GMIN11. GMAX*** = 20 x log (VMAX*** / V100) GMIN*** = 20 x log (VMIN*** / V100) [dB] [dB]
Note: When a spectrum analyzer is used, measure gain for low frequency.
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Note No. P22 Characteristics SW71 Sharpness control center characteristic B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. 5. 6. 7. 8. 9. Input sine wave to TPA. (The frequency is variable.) Set the amplitude of #68 to 20 mVp-p. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M (00), and color detail enhancer (CDE) to center (10). Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #12. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V100. Set picture sharpness to center (1000000). Set input frequency to FAP00, measure #12 amplitude VCEN00, and calculate GCEN00 using the following equations. Set APACON peak frequency to 9.5 M (01). Set input frequency to FAP01, measure VCEN01 and calculate GCEN01. Set APACON peak frequency to 6.4 M (10). Set input frequency to FAP10, measure VCEN10 and calculate GCEN10. Set APACON peak frequency to 4.5 M (11). Set input frequency to FAP11, measure VCEN11 and calculate GCEN11. GCEN*** = 20 x log (VCEN*** / V100) [dB]
Note: When a spectrum analyzer is used, measure gain for low frequency.
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Note No. P23 Characteristics SW71 2T pulse response SRT control B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. 5. 6. 7. 8. Input 2T pulse (0.7 Vp-p) signal to TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10) picture sharpness control to center (1000000). Set APACON peak frequency to13.5 M (00), and monitor #12. Measure TSRTMIN00 and VSRTMIN00 as shown in the figure below. Set SRT-GAIN to maximum (11111), and measure TSRTMAX00 and VSRTMAX00. Set APACON peak frequency to 9.5 M (01). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN01/VSRTMIN01 and TSRTMAX01/ VSRTMAX01. Set APACON peak frequency to 6.4 M (10). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN10/VSRTMIN10 and TSRTMAX10/ VSRTMAX10. Set APACON peak frequency to 4.5 M (11). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN11/VSRTMIN11 and TSRTMAX11/VSRTMAX11. Calculate the following equations. TSRT00 = 20 x log [((VSRTMAX00/TSRTMAX00)/(VSRTMIN00/TSRTMIN00)) TSRT01 = 20 x log [(VSRTMAX01/TSRTMAX01)/(VSRTMIN01/TSRTMIN01)] TSRT10 = 20 x log [(VSRTMAX10/TSRTMAX10)/(VSRTMIN10/TSRTMIN10)] TSRT11 = 20 x log [(VSRTMAX11/TSRTMAX11)/(VSRTMIN11/TSRTMIN11)]
T***
20%
V***
100%
20%
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Note No. P24 Characteristics SW71 VSM gain B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. Input sine wave of FVSM frequency to TPA. Set #68 amplitude to 0.02 Vp-p. Turn on SW77 and change VSM gain from minimum (001) to maximum (111). Measure #77 amplitude, V001, V011, V100, V101, V110, and V111. Set input amplitude to 0.7 Vp-p, and VSM gain to OFF (000). Measure TP77 amplitude V000. Calculate the following equations. GV000 = 20 x log (V000/0.7) [dB] GV001 = 20 x log (V001/0.02) [dB] GV010 = 20 x log (V010/0.02) [dB] GV011 = 20 x log (V011/0.02) [dB] GV100 = 20 x log (V100/0.02) [dB] GV101 = 20 x log (V101/0.02) [dB] GV110 = 20 x log (V110/0.02) [dB] GV111 = 20 x log (V111/0.02) [dB] P25 VSM limit B B B A ON 1. 2. 3. Input sine wave of frequency FVSM to TPA. Set VSM gain to 111, and #68 amplitude to 0.7 Vp-p. Turn on SW77 and measure TP77 amplitude VLU and VLD [Vp-p] as shown in the figure below.
3.
VLU
VLD
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Note No. P26 Characteristics SW71 Y delay time switching B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and input 2T pulse signal (approximately 0.7 V (p-p)) to TPA. Set picture sharpness to center (1000000). Monitor #68 and #12 as shown in the figure below. Measure YDL00 that is the time difference between signals #68 and #12. Set Y/C-DL1 to +5 ns (1), and measure YDL01 as shown in the figure below. Set Y/C-DL1 to 0 ns (0), Y/C-DL2 to +10 ns (1) and measure YDL10 as shown in the figure below. Set Y/C-DL1 to +5 ns (1), Y/C-DL2 to +10 ns (1) and measure YDL11 as shown in the figure below. Determine YDLA, YDLB, and YDLC using the following equations. YDLA = YDL01 - YDL00 YDLB = YDL10 - YDL00 YDLC = YDL11 - YDL00 YDL00 YDL01 YDL10 YDL11 50%
5.
2T pulse Approximately 0.7 Vp-p
6.
#12 #68 50%
7.
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Note No. P27 Characteristics SW71 Y group delay correction B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. Input Multi Burst signal (4.2-MHz frequency, 0.1 Vp-p at #68) of A signal in TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and Color detail enhancer (CDE) to minimum (00000). Set sharpness to flat (DEC [30]), APACON peak frequency to 4.5 M (11), and monitor #12. Sine wave signal A input becomes like signal B on #12 as shown in the figure on the right. Measure SA and SB. When group delay correction is set to minimum (0000), signal A becomes like signal C on #12. Measure SAMIN and SBMIN. When group delay correction is set to maximum (1111), signal A becomes like signal D on #12. Measure SAMAX and SBMAX. Calculate the following equations. GAMIN = 20 x log (SAMIN/SA) [dB] GBMIN = 20 x log (SBMIN/SB) [dB] GAMAX = 20 x log (SAMAX/SA) [dB] GBMAX = 20 x log (SBMAX/SB) [dB] Signal C SAMIN
3.
Signal A
4.
SA Signal B SB
5.
6.
SBMIN
SAMAX Signal D
SBMAX
Note: Sine wave input starts and ends within the picture period such as a burst signal. The wave is not continuous.
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Note No. P28 Characteristics SW71 Color detail enhancer (CDE) B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), color to center (1000000), and color limiter level to 2 Vp (1). Input SWEEP signal to TPA so that #68 amplitude is 20 mVp-p. Set SW67 to A, and input signal as shown in the figure below (#67 amplitude is 0.2 Vp-p) to TP67. Set picture sharpness to center (1000000), Y detail control to center (1000), and monitor #14 with a spectrum analyzer. When CDE is at minimum (00), set low frequency area to 0dB, and determine peak level GCDEMIN. When CDE is at maximum (11), set low frequency area to 0dB, and determine peak level GCDEMAX. Calculate the following equation. GCDE00 = GCDEMAX00 - GCDEMIN00 When APACON peak frequency is 13.5 M (00), 9.5 M (01), 6.4 M (10), and 4.5 M (11), calculate GCDE00, GCDE01, GCDE10, and GCDE11 respectively using above equation.
2. 3. 4. 5. 6.
Output gain [dB]
max 0.2 Vp-p min 0dB BLK period picture period
Input frequency [MHz]
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Note No. P29 Characteristics SW71 Y detail control range B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW74 ON 1. 2. 3. 4. 5. 6. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10), and APACON peak frequency to 4.5 M (11). Input SWEEP signal to TPA. Set #68 amplitude to 20mVp-p. Set picture sharpness to center (1000000), Y detail control to maximum (1111), and monitor #12 with a spectrum analyzer. Set low frequency area to 0dB, and measure each peak level GYDMAX. Set Y detail control to center (1000), and measure peak level GYDCEN. Set Y detail control to minimum (0000), and measure peak level GYDMIN.
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Test Conditions for Color Difference Block 1: YUV input and matrix
Common Test Condition for Color Difference Block 1: YUV input and matrix
1. 2. 3. 4. SW71 = B, SW70 = B, SW44 = ON, SW18 to SW26 = A, SW77 = OPEN, SW74 = OPEN Transfer BUS control data with preset values. Turn ACB operation switching to ACB OFF (0), and turn high blight color OFF (0). Input sync signal [must be sync with input signal for testing except Sweep.] to #53 (sync input), and set SYNC-IN-SW to 1.
Test Conditions SW Mode SW67 SW66 A SW61 B A SW60 B 2. 3.
Note No. S01
Characteristics SW68 Color SRT gain C SW63 B
Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW64 B 1. Set Y mute ON (P-MODE: Y-MUTE, 001), brightness to center (10000000), color to center (1000000), unicolor to maximum (1111111). Input 2T pulse signal to TP67 so that #67 amplitude is 423 mVp-p. Monitor #14 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11) that are SB00MIN, SB00CEN, and SB00MAX as shown in the figure below. Set SB00MIN to 0dB, calculate GSB00CEN = 20 x log (SB00CEN/SB00MIN) and GSB00MAX = 20 x log (SB00MAX/SSB00MIN). When color SRT peak is 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11). Calculate GSB01CEN and GSB01MAX. Input 2T pulse signal to TP66 so that #66 amplitude is 300 mVp-p. Monitor #12 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11) that are SR00MIN, SR00CEN, and SR00MAX as shown in the figure below. Set SR00MIN to 0dB, calculate GSB00CEN = 20 x log (SB00CEN/SB00MIN) and GSB00MAX = 20 x log (SB00MAX/SSB00MIN). T*** When color SRT peak is 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11). Calculate GSR01CEN and GSR01MAX. Gradient 20% S*** = V***/T***
4. 5. 6.
7.
V***
100%
20%
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Note No. S02 Characteristics SW68 Dynamic Y/C compensation C SW63 B Test Conditions SW Mode SW67 SW66 A SW61 B A SW60 B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW64 B 1. Input 100-kHz sync signal to TP67, and set #67 amplitude to 0.2 Vp-p. Set Y mute OFF (P-MODE: Normal 1, 000), brightness to center (1000000), color to center (1000000), unicolor to maximum (1111111), and Y/C Gain Comp to minimum (00). Set black stretch point 1 to OFF (000), dark area static Y gain to minimum (00), light area static Y gain to maximum (11), and SW1 to B. Apply 5.16 V to #68 from external power supply PS1. Monitor #14 output waveform, and measure amplitude VBDY0. Set Y/C Gain Comp to maximum (11). Set SW1 to B. Set black stretch point 1 to OFF (000), dark area static Y gain to maximum (11), light area static Y gain to maximum (00), and monitor #14 amplitude VBDY1. Set Y/C Gain Comp to maximum (11). Switch SW1 to A, and TPI to GND. Set black stretch point 1 to maximum (111), dark area static Y gain to minimum (00), bright area static Y gain to maximum (11), and monitor #14 amplitude VBDY2. Calculate the following equations. GCBDY1 = 20 x log (VBDY1/VBDY0), GCBDY2 = 20 x log (VBDY2/VBDY0) 7. Input 100-kHz sync signal to TP5, and repeat the procedure above. Calculate the following equations. GCRDY1 = 20 x log (VRDY1/VRDY0), GCRDY2 = 20 x log (VRDY2/VBDY0)
SW74 2. OPEN 3. 4. 5.
6.
71
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Note No. S03 YUV gain Characteristics SW68 A/C SW8 B Test Conditions SW Mode SW67 SW66 A/B SW9 B A/B SW10 B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW64 B SW56 OPEN 2. 3. 4. 5. 6. 7. 8. 9. 1. Set picture mute to OFF (P-MODE: Normal 1, 000), brightness to maximum (11111111), color to center (1000000), and unicolor to maximum (1111111). Set SW68 to A. Set SW67 and SW66 to B, and input 100-kHz sine wave to TPA. Set #68 amplitude to 0.2 Vp-p. Set SW74 open. Measure #74 amplitude VY00 and VY01 when Y/color difference input mode is set to Y/Cb/Cr (0) and Y/Pb/Pr (1). Set SW68 to C, SW67 to A, and SW66 to B. Input 100-kHz sine wave to TP67, and set #67 amplitude to 0.2 Vp-p. Measure #14 amplitude VB00 when Y/color difference input mode is set to Y/Cb/Cr (0). Measure #14 and #12 amplitude VBB01 and VBR01 when Y/color difference input mode is set to Y/Pb/Pr (1). Set SW68 to C, SW67 to B, and SW66 to A. Input 100-kHz sine wave to TP66, and set #66 amplitude to 0.2 Vp-p. Measure #12 amplitude VR00 when Y/color difference input mode is set to Y/Cb/Cr (0). Measure #14 and #12 amplitude VRB01 and VRR01 when Y/color difference input mode is set to Y/Pb/Pr (1).
10. Calculate the following equations. GY00 = 20 x log (VY00/0.2), GY01 = 20 x log (VY01/0.2) GCBB = 20 x log (VB00/0.2), GPBB = 20 x log (VBB01/0.2), GPBR = 20 x log (VBR01/0.2) GCRR = 20 x log (VR00/02), GPRB = 20 x log (VRB01/0.2), GPRR = 20 x log (VRR01/0.2)
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Note No. S04 Characteristics SW68 Green stretch C SW26 A SW19 A Test Conditions SW Mode SW67 SW66 A SW25 A SW18 A A SW24 A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 3C) SW64 1. Input signal B as shown in the figure below from TP67 (Cb/Pb1 input), and signal A from TP66 (Cr/Pr input). Set brightness [06] to maximum (FF). Measure amplitudes A, B, C, D, and E at #13 (Gout) as shown in the figure below. (A00 to E00) Set green stretch [14] data to (08), and repeat the step 3 above. (A01 to E01) Set green stretch [14] data to (10), and repeat the step 3 above. (A10 to E10) Set green stretch [14] data to (18), and repeat the step 3 above. (A11 to E11) Green stretch gain is calculated by the following equations A01 A00 B01 GrB01= B00 C01 GrC01 = C00 D01 GrD01 = D00 E01 GrE01= E00 GrA01 = A10 A00 B10 GrB10 = B00 C10 GrC10 = C00 D10 GrD10 = D00 E10 GrE10 = E00 GrA10 = 0.05 Vp-p Signal A 0 Vp-p -0.05 Vp-p -0.087 Vp-p -0.1 Vp-p 0 Vp-p -0.07 Vp-p -0.122 Vp-p -0.122 Vp-p -0.14 Vp-p B C A Pin 13 150 180 D 210 240 E 270 A11 A00 B11 GrB11 = B00 C11 GrC11 = C00 D11 GrD11 = D00 E11 GrE11= E00 GrA11=
SW21 2. A 3. 4. 5. 6. 7.
Signal B
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Test Conditions for Color Difference Block 2
Common Test Conditions for Color Difference Block 2
1. 2. 3. SW71 = B, SW70 = B, SW61 to SW63 = B, SW44 = ON, SW40 = B Unless otherwise specified, measure each bus data with preset values. Set the following data. Subaddress (00) Data (02) Subaddress (02) Data (0C) Subaddress (05) Data (7F) Subaddress (06) Data (6C) Subaddress (07) Data (40) Subaddress (0B) Data (7F) Subaddress (0C) Data (84) Subaddress (12) Data (F0) Subaddress (13) Data (F0) Subaddress (15) Data (00) Subaddress (18) Data (00) Subaddress (1A) Data (C0) Subaddress (1B) Data (E0) Subaddress (1C) Data (03) Subaddress (1D) Data (78)
Test Conditions SW Mode SW26 SW25 SW24 A A A
Note No. A01
Characteristics SW68 Color difference contrast adjustment characteristic C SW67 A or B SW66 A or B
Test Method SW21 A SW19 A SW18 A 1. 2. 3. Set brightness to maximum, and subaddress (12) data to (F0). Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.23 Vp-p) from pin 66. Change unicolor data to maximum (7F), center (40), and minimum (00), and measure pin 12 picture period amplitude VuCYMAX, VuCYCNT, and VuCYMIN respectively. Determine unicolor amplitude ratio between maximum and minimum in decibels. (VuCY) Repeat the steps 2 to 4 above with the following pins: Input (picture period amplitude 0.2 Vp-p) from pin 67, and measure pin 14.
4. 5.
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Note No. A02 Characteristics SW68 Color adjustment characteristic C SW67 A or B SW66 A or B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. Set brightness to maximum, and subaddress (12) data to (F0). Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.115 Vp-p) from pin 66. Change color data to maximum (7F), center (40), and minimum (01), and measure pin 12 picture period amplitudes VCCYMAX VCCYCNT, and VCCYMIN respectively. Calculate amplitude ratios of maximum and minimum against color center in decibels. (VCCY) Repeat the steps 2 to 4 above with the following pins: Input (picture period amplitude 0.1Vp-p) from pin 67 and measure pin 14. Input signal 3 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 66. Measure pin 12 output picture period amplitude vHTARY. Apply 1.5 V to pin 79 from external power supply. Measure pin 12 output picture period amplitude vHTBRY. Calculate GHTRY = vHTBRY/vHTARY Repeat the steps 1 to 5 above and measure pin 13. Calculate GHTGY = vHTBGY/vHTAGY Repeat the steps 1 to 5 above and measure pin 67. Calculate GHTBY = vHTBBY/vHTABY.
4. 5. A03 Color difference halftone characteristic C A or B A or B A A A A A A
1. 2. 3. 4. 5. 6. 7.
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Note No. A04 Characteristics SW68 Color characteristic C SW67 B SW66 A Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. Input signal 2 from pin 66. Increase signal 2 amplitude A. Determine gamma correction point V1, V2, and V3 of subaddress data (14). Set subaddress (14) data as follows: (01) - OFF (03) -1ON (05) -2ON (07) -3ON Measure #12 output signal amplitude levels and chart a characteristic diagram. 3. Determine V where starts applying and gradient at ON when linearity at OFF is 1.
#12 output amplitude
OFF
V
ON
#66 input amplitude
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Note No. A05 Characteristics SW68 Color limiter characteristic C SW67 B SW66 A Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. C B A A A A A A A 1. 2. 3. 4. Input signal 2 (picture period amplitude = 0.56 Vp-p) from pin 67. Set subaddress (14) to (00)/(01), and measure pin 12 output signal picture period amplitude, CLT0/CLT1. Input signal 2 (picture period amplitude = 0.28 Vp-p) from pin 67. Adjust color so that pin 14 output picture period amplitude is 1.2 Vp-p. Set subaddress (0B) data to (80) and measure pin 14 output signal picture period amplitude v14. Calculate the following equation. HBC1 = (1.2 - v14)/1.2
A06
High-bright color gain
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Test Conditions for Text Block
Common Test Conditions for Text Block
1. 2. 3. SW71 = B, SW70 = B, SW60 to SW64 = B, SW44 = ON, SW40 = B Unless otherwise specified, measure each bus data with preset values. Set the following data. Subaddress (00) Data (02) Subaddress (02) Data (0C) Subaddress (05) Data (7F) Subaddress (06) Data (6C) Subaddress (07) Data (40) Subaddress (0B) Data (7F) Subaddress (0C) Data (84) Subaddress (12) Data (F0) Subaddress (13) Data (F0) Subaddress (15) Data (00) Subaddress (18) Data (00) Subaddress (1A) Data (C0) Subaddress (1B) Data (E0) Subaddress (1C) Data (03) Subaddress (1D) Data (78)
Test Conditions SW Mode SW26 SW25 SW24 A A A
Note Characteristics No. T01 AC gain
Test Method SW21 A SW19 A SW18 A 1. 2. 3. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Measure pins 12, 13, and 14 picture period amplitude, V12, V13, and V14. Calculate AC gain using the following equations. GR = V12/0.2 GG = V13/0.2 GB = V14/0.2
SW68 A
SW67 B
SW66 B
T02
Unicolor adjustment characteristic
A
B
B
A
A
A
A
A
A
1. 2. 3.
Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Change unicolor data to maximum (7F), center (40), and minimum (00) and measure pin 12 picture period amplitude, VuMAX, VuCNT, and VuMIN respectively. Calculate amplitude ratio of VuMAX and VuMIN in decibels (Vu) Input signal 2 from pin 68 and adjust pin 12 picture period output amplitude to 1 Vp-p. Change brightness data to maximum (7F), center (80), and minimum (00) and measure pin 12 voltages, VbrMAX, VbrCNT, and VbrMIN respectively.
T03
Brightness adjustment characteristic
A
B
B
A
A
A
A
A
A
1. 2.
78
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Note Characteristics No. T04 White peak slice level SW68 C SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. T05 Black peak slice level RGB output S/N C B B A A A A A A 1. 2. C B B A A A A A A 1. 2. 3. 4. Set subcontrast to maximum. Apply external power supply to pin 68 and gradually increase voltage from 5.8 V. When picture period of pin 12 is clipped, measure pin 12 picture period amplitude voltage, Vwps1. Change subaddress (0C) data to (FC) and repeat the steps 1 to 3 above. (Vwps2) Apply external power supply to pin 68 and gradually decrease voltage from 5.8 V. When picture periods are clipped, measure pins 14, 13, and 12 voltage, Vbps. Adjust brightness data so that picture period voltage of pin 14 is 2.4 V. Set color data to minimum. Measure noise levels n14-, n13-, and n12-Vp-p in picture period of pin 14, 13, and 12 with an oscilloscope. Calculate S/N. N14 = -20 x log [2.3/(0.2 x n14)] N13 = -20 x log [2.3/(0.2 x n13)] N12 = -20 x log [2.3/(0.2 x n12)] T07 Halftone characteristic A B B A A A A A A 1. 2. 3. 4. 5. 6. 7. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 68. Measure pin 14 picture period amplitude v14A. Apply 1.5 V to pin 79 from external power supply. Measure pin 14 picture period amplitude v14B Calculate the following equation. GHT1 = v14B/v14A Stop applying voltage to pin 79. Set subaddress (1A) to data (E2) and measure pin 14-picture period amplitude, v14C. Calculate the following equation. GHT2 = v414C/v14A
T06
79
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Note Characteristics No. T08 BLK pulse delay time SW68 C SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. Apply signal shown in the figure (A) below to pin 39 (BLK input), and measure tdON and tdOFF of output signals from pins 12, 13, and 14 shown in the figure (B) below. 63.5 s
(A) Appling signal to pin 39
tdON
tdOFF
(B) Output signal from pins 12, 13, and 14
80
2003-01-21
TA1360AFG
Note Characteristics No. T09 Drive adjustment variable range SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. 6. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 68. Measure picture period amplitude of pin 13 when subaddress (0D) data is changed to maximum (FE), center (80), and minimum (00). Use picture period amplitude at center as the base. Determine amplitude ratio DRG1+ and DRG1- at maximum and minimum in decibels. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 14, DRB1+ and DRB1- in decibels when subaddress (0E) data is changed. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 13, DRG2+ and DRG2- in decibels when subaddress (0E) center data is set to (81) used as the base. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 14, DRB2+ and DRB2- in decibels when subaddress (0E) data is changed to maximum (FF), center (81), and minimum (01). Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 12, DRR1+ and DRR2- in decibels when subaddress (0D) data is changed to maximum (FF), center (81), and minimum (01). Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 14, DRB3+ and DRB3- in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data is changed. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 13, DRG3+ and DRG3- in decibels when subaddress (0E) data is set to (81), and subaddress (0D) data is changed to maximum (FF), center (81), and minimum (01).
7.
8.
9.
10. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 12, DRR2+ and DRR2- in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data is changed to maximum (FF), center (81), and minimum (01). T10 #78 input impedance C B B A A A A A A 1. 2. 3. Connect external power supply, an ammeter, and a voltmeter to pin 78. Adjust voltage so that current value is set to zero. Measure the current when voltage of pin 78 is increased by 0.2V. (lin) Calculate the following equation. in53 = 0.2 V/Iin () 78 - A +
Ammeter (A)
V
Voltmeter
81
2003-01-21
TA1360AFG
Note Characteristics No. T11 ACL characteristic SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 68. Measure pin 12 picture period amplitude, vACL1. Apply "DC voltage of pin 78 - 0.8 V" to pin 78 from external power supply and measure pin 12-picture period amplitude, vACL2. Apply "DC voltage of pin 78 - 1.3 V" to pin 78 from external power supply and measure pin 12-picture period amplitude, vACL3. Calculate the following equations. ACL1 = -20 x log (vACL2/vACL1) ACL2 = -20 x log (vACL3/vACL1) T12 ABL point C B B A A A A A A 1. 2. 3. 4. Measure DC voltage of pin 78, VABL1. Set subaddress (1B) data to (1C). Apply external voltage to pin 78, and decrease voltage from 6.5 V. When voltage of pin 12 starts changing, measure pin 78 voltage, VABL2. Change subaddress (1B) data to (3C), (5C), (7C), (9C), (BC), (DC), and (FC) under the status of the step 3 above. Measure pin 78 voltage: VABL3, VABL4, VABL5, VABL6, VABL7, VABL8, and VABL9. ABLP1 = VABL2 - VABL1 ABLP5 = VABL6 - VABL1 ABLP2 = VABL3 - VABL1 ABLP6 = VABL7 - VABL1 ABLP3 = VABL4 - VABL1 ABLP7 = VABL8 - VABL1 ABLP4 = VABL5 - VABL1 ABLP8 = VABL9 - VABL1
5.
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Note Characteristics No. T13 ABL gain SW68 C SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. Apply 6.5-V external voltage to pin 78. Set subaddress (1B) data to (00). Set brightness data to maximum. Apply 4.5-V external voltage to pin 78. Change subaddress (1B) data to (00), (04), (08), (0C), (10), (14), (18), and (1C). Repeat the step 3 above, and measure VABL11, VABL12, VABL13, VABL14, VABL15, VABL16, VABL17, and VABL18. ABLG1 = VABL11 - VABL10 ABLG2 = VABL12 - VABL10 ABLG3 = VABL13 - VABL10 ABLG4 = VABL14 - VABL10 ABLG5 = VABL15 - VABL10 ABLG6 = VABL16 - VABL10 ABLG7 = VABL17 - VABL10 ABLG8 = VABL18 - VABL10 T14 RGB output mode C B B A A A A A A 1. 2. 3. 4. 5. Adjust brightness data so that picture period voltage of pin 12 is 2.4 V. Set subaddress (1B) data to (01). Measure pins 12, 13, and 14 picture period voltage, V12R, V13R, and V14R. Set subaddress (1B) data to (02), and repeat the step 3 above. Measure pins 12, 13, and 14 picture period voltage, V12G, V13G, and V14G. Set subaddress (1B) data to (03), and repeat the step 3 above. Measure pins 12, 13, and 14 picture period voltage, V12B, V13B, and V14B.
6.
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Note Characteristics No. T15 Y-OUT characteristic SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. Input RAMP waveform from pin 68. Adjust input amplitude so that picture period amplitude of pin 12 is 2.3 Vp-p. Set subaddress (0C) data to (81). Adjust input amplitude so that picture period amplitude of pin 12 is 2.3 Vp-p. Monitor pin 12. According to the figure below, determine Y-OUT correction start points 1 and 2. Also determine ratios of gradients at Y-OUT ON to Y-OUT OFF in decibel. (1, 2, and 3) Output amplitude (Y-OUT)
100 IRE 3 2 2
1 1
2.3 Vp-p
Note: Solid line indicates gamma OFF. Dotted line indicates gamma ON.
Input amplitude
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2003-01-21
TA1360AFG
Note Characteristics No. T16 White-peak blue characteristic SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. 6. 7. 8. Input 0.7-Vp-p RAMP signal from pin 68. Set subcontrast data to maximum. Set subaddress (1F) data to (04). Set subaddress (1E) data to (01), and monitor pin 14. Determine blue stretch start point BSPmin using the figure below. Repeat the step 4 above by changing subaddress (1E) data to (04) and (07). Determine blue stretch start point BSPCNT and BSPmax. Set subaddress (1E) data to (04). Monitor pin 14 and calculate ratio of blue stretch ON gradient in relative to blue stretch OFF gradient in decibel (BSGCNT) using the figure below. Repeat the step 7 above by changing subaddress (1F) data to (00) and (07). Calculate gradient ratio in decibel (BSGmin and BSGmax).
Note: Calculate white-peak blue start point in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. ON Output (Output from pin 14)
OFF
Start point
Input amplitude
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2003-01-21
TA1360AFG
Note Characteristics No. T17 ACB insertion pulse phase and amplitude SW68 A or C 2. 3. 4. SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set brightness data to 108. Measure pins 4, 6, and 7 voltage. Apply measured voltages from external power supply. Set subaddress (02) data to (40). Use output signals from pins 12, 13, and 14, and measure ACB insertion pulse phase as shown in the Figure 1.
Note: Take picture period following FBP input fall after V BLK, count the phase as 2H, 3H, and so on.
BLK ends as phase 1H. After next H
ACB insertion pulse
V BLK period
Figure 1: RGB Output 1H 2H 3H 4H
Figure 2: FBP Input (#39)
5. 6. 7.
Monitor pins 12, 13, and 14. Measure ACB insertion pulse amplitudes (level from picture period amplitude at quiescent.): VACB1R, VACB1G, and VACB2B. Set subaddress (02) data to (80), and repeat the step 5 above: VACB2R, VACB2G, and VACB2B. Set subaddress (02) data to (C0), and repeat the step 5 above: VACB3R, VACB3G, and VACB3B.
86
2003-01-21
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Note Characteristics No. T18 IK input amplitude SW68 A or C 2. 3. SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set subaddress (02) data to (40). Measure voltage amplitude of pin-8 input signal in ACB insertion period. 1H = IKR T19 IK input cover range C B B A A A A A A 1. 2. 3. 4. 5. 6. 7. 8. T20 Analog RGB gain A B B A or B A or B A or B 2. 3. 4. 5. A A A 1. 2H = IKG 3H = IKB
Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set subaddress (02) data to (40). Measure pin 8 DC voltage in V BLK period. (#8VBLK) Apply the current externally to pin 8. Measure DC voltage of pin 8 in V BLK period when pin-12 picture period voltage begins to be decreased. (#8VBLK+) Apply current outward from pin 8. Measure DC voltage of pin 8 in V BLK period when pin-12 picture period voltage begins to be increased. (#8VBLK-) DIKin+ = (#8VBLK+) - (#8VBLK) DIKin- = (#8VBLK-) + (#8VBLK) Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pin 2. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 24. Measure pin 12 picture period amplitude, v12R. Repeat the steps 3 and 4 above with the following pins: Input from pin 25, and measure output from pin 13 (v13G). Input from pin 26, and measure output from pin 14 (v14B). Calculate the following equations. GTXR = v12R/0.2 GTXG = v13G/0.2 GTXB = v14B/0.2 Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pin 2. Set RGB contrast data to maximum (7F). Input signal 2 to pin 24. Gradually increase picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. Repeat the steps 3 and 4 above with following pins: Input from pin 25 and measure output from pin 13. Input from pin 26 and measure output pin 14.
6 T21 Analog RGB white peak slice level A B B A A A A A A 1. 2. 3. 4. 5.
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Note Characteristics No. T22 Analog RGB black peak limit level SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. T23 RGB contrast adjustment characteristic A B B A or B A or B A or B 2. 3. 4. 5. 6. T24 Analog RGB brightness adjustment characteristic A B B A or B A or B A or B 2. 3. 4. 5. A A A 1. A A A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pin 2. Set RGB contrast data to maximum (7F). Input signal 2 to pin 24. Gradually decrease picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. Repeat the step 4 above with the following pins: Input from pin 25 and measure output from pin 13. Input from pin 26 and measure output pin 14. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pin 2. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 24. RGB contrast data to maximum (7F), center (40), and minimum (00). Measure pin 12 picture period amplitudes VuTXR (maximum, center, and minimum) respectively. Calculate amplitude ratio of maximum and minimum in decibels. Repeat the steps 4 and 5 above with the following pins: Input from pin 25 and measure pin 13. Input from pin 26 and measure pin 14. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Input signal 2 from pins 26, 25, and 24. Apply 5-V external voltage to pin 2. Adjust amplitude A of signal 2 so that picture period amplitude of pin 12 is 0.5 Vp-p. Change RGB brightness data to maximum (FE), center (80), and minimum (00). Measure pins 12, 13, and 14 picture period voltage VbrTX (maximum, center, and minimum) respectively. Set RGB brightness data to maximum (FE). Input signal 4 (signal amplitude = 1.5 Vp-p) from pin 2. Measure input/output transfer characteristics using pin 12 according to the figure T-2. Repeat the steps 2 and 3 above with the following pins: Input from pin 25 and measure pin 13. Input from pin 24 and measure pin 14. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above.
T25
Analog RGB mode switching transfer characteristic
C
B
B
A
A
A
A
A
A
1. 2. 3. 4. 5.
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Note Characteristics No. T26 Text ACL characteristic SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A B Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. 6. 7. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pin 2. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 24. Measure pin 12 picture period amplitude, vTXACL1. Apply "pin 78 DC voltage - 0.8 V" to pin 78 from external power supply, and measure pin 12-picture period amplitude, vTXACL2. Apply "pin 78 DC voltage - 1.3 V" to pin 78 from external power supply, and measure pin 12-picture period amplitude, vTXACL3. TXACL1 = -20 x log (vTXACL2/vTXACL1) TXACL2 = -20 x log (vTXACL3/vTXACL1) T27 Analog OSD gain A B B A A A A or B A or B A or B 2. 3. 4. 5. 6. T28 Analog OSD input white peak slice level A B B A A A A A A 1. 2. 3. 4. T29 Analog OSD black peak limit level A B B A A A A A A 1. 2. 3. 4. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pins 1 and 80. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18. Measure pin 12 picture period amplitude, v12R. Repeat the steps 3 and 4 above with the following pins: Input from pin 19, and measure pin 13. Input from pin 21 and measure pin 14. (v13G and v14B) Calculate the following equations. GOSDR = v12R/0.2 GOSDG = v13G/0.2 GOSDB = v14B/0.2 Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pins 1 and 80. Input signal 2 from pin 18. Gradually increase picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. Repeat the step 3 above with the following pins: Input from pin 19, and measure pin 13. Input from pin 21, and measure pin 14. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pins 1 and 80. Input signal 2 from pin 18. Gradually decrease picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. Repeat the step 3 above with the following pins: Input from pin 19, and measure pin 13. Input from pin 21, and measure pin 14.
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2003-01-21
TA1360AFG
Note Characteristics No. T30 OSD contrast adjustment characteristic SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A or B SW19 A or B SW18 A or B 2. 3. 4. 5. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pins 1 and 80. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18. Change OSD contrast data to (11), (10), (01), and (00). Measure pin 12 picture period amplitude VuOSDR (11), (10), (01), and (00) respectively. Repeat the steps 3 and 4 above with the following pins: Input from pin 19, and measure pin 13, VuOSDG (11), (10), (01), and (00). Input from pin 21, and measure pin 14, VuOSDB (11), (10), (01), and (00). Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pins 1 and 80. Change OSD brightness data (subaddress 1D) to (38), (78), (B8), and (F8), and measure picture period voltage of pins 12, 13, and 14 respectively. Data (38) = VbrOSD0 Data (78) = VbrOSD1 Data (B8) = VbrOSD2 Data (F8) = VbrOSD3 T32 Analog OSD mode switching transfer characteristic C B B A A A A A A 1. 2. 3. 4. 5. 6. Set OSD brightness data to maximum (11). Input signal 4 (signal amplitude = 4.5 Vp-p) from pin 1. Measure input/output transfer characteristics using pin 12 according to the figure T-2. Repeat the steps 2 and 3 above, and measure pins 13 and 14. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above. Repeat the steps 1 to 5 above with the following pin. Input signal 4 (signal amplitude 4.5 Vp-p) from pin 80.
T31
Analog OSD brightness adjustment characteristic
C
B
B
A
A
A
A
A
A
1. 2. 3.
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TA1360AFG
Note Characteristics No. T33 OSD ACL characteristic SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 B 1. 2. 3. 4. 5. 6. 7. 8. 9. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set subaddress (07) data to (01). Apply 5-V external voltage to pins 1 and 80. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18. Measure pin 12 picture period amplitude, vOSDACL1. Apply "pin 78 DC voltage - 0.8 V" to pin 78 from external power supply, and measure pin 12-picture period amplitude, vOSDACL2. Apply "pin 78 DC voltage - 1.3 V" to pin 78 from external power supply, and measure pin 12-picture period amplitude, vOSDACL3. OSDACL1 = -20 x log (vOSDACL2/vOSDACL1) OSDACL2 = -20 x log (vOSDACL3/vOSDACL1) OSDACL3 OSDACL4 Change subaddress (07) data to (80), and repeat the steps 6 to 8 above to measure OSDACL3 and OSDACL4.
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Note Characteristics No. T34 OSD blending characteristic SW68 A C SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A B SW19 A B SW18 B B 1. 2. 3. 4. 5. 6. 7. 8. 9. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Measure pins 14, 13, and 12 picture period amplitude, v14a, v13a, and v12a. Apply 5-V external voltage to pin 80. Measure pins 14, 13, and 12 picture period amplitude, v14b, v13b, and v12b. Calculate v14b amplitude in relation to v14a, v13b amplitude in relation to v13a, and v12b amplitude in relation to v12a in decibel: 14TV1, 13TV1, and 12TV1. Apply 5-V external voltage to pin 1, and repeat the steps 3 to 5 above: 14TV2, 13TV2, and 12TV2. Apply 5-V external voltage to pins 1 and 80, and repeat the steps 3 to 5 above: 14TV3, 13TV3, and 12TV3. Set SW68 to C. Set SW21, 19, and 18 to B. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pins 21, 19, and 18.
10. Apply 5-V external voltage to pins 1 and 80. 11. Measure pins 14, 13, and 12 picture period amplitude, v14c, v13c, and v12c. 12. Apply 5-V external voltage to pin 1. 13. Measure pins 14, 13, and 12 picture period amplitude, v14d, v13d, and v12d. 14. Calculate v14d amplitude in relation to v14c, v13d amplitude in relation to v13c, and v12d amplitude in relation to v12c in decibel: 14OSD1, 13OSD1, and 12OSD1. 15. Apply 5-V external voltage to pin 80, and repeat the steps 12 to 14 above: 14OSD2, 13OSD2, and 12OSD2. 16. Apply 5-V external voltage to pins 1 and 80, and repeat the steps 12 to 14 above: 14OSD3, 13OSD3, and 12OSD3.
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Note Characteristics No. T35 Blue stretch point/gain SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. 6. 7. 8. Input RAMP signal 0.7 Vp-p from pin 68. Set subcontrast data to maximum. Set subaddress (15) data to (0C). Set subaddress (1A) data to (C0), monitor pin 14, and measure blue stretch start point using the figure below (BLPmin). Set subaddress (1A) data to (CC), and repeat the step 4 above. (BLPmax) Set subaddress (1A) data to (C4). Monitor pin 14 and measure gradient at blue stretch ON in decibel in relation to the one at blue stretch OFF according to the figure below. (BLGmax) Set subaddress (15) data to (04), and repeat the step 7 above. (BLGmin)
Note: Calculate blue stretch start point in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. Output amplitude Blue stretch ON
Blue stretch OFF
Input amplitude
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TA1360AFG
Note Characteristics No. T36 Blue stretch gamma correction SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. 5. Input RAMP signal 0.7 Vp-p from pin 68. Set subcontrast data to maximum. Set subaddress (15) data to (08). Set subaddress (09) data to (81). Monitor pin 14 and measure amplitude of the intersection point of blue stretch OFF and blue stretch ON according to the figure below. Calculate pin 14 output amplitude in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. Set subaddress (1A) data to (C4), (C8), and (CC). Repeat the step 5 above. (BL2, BL3, and BL4) Output amplitude Blue stretch OFF BL Intersection poiint Blue stretch ON
6.
Input amplitude
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TA1360AFG
Note Characteristics No. T37 White letters improvement SW68 A SW67 B SW66 B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 A SW19 A SW18 A 1. 2. 3. 4. Apply a pulse to pin 68 as shown in Figure A. Monitor # 12 output waveform. Plot # 12 output amplitude when changing # 68 input signal amplitude from 0 to 120 IRE (0.857 Vp-p) (See Figure B below). Set subaddress (19) data to (80). Monitor # 12 output waveform. Plot # 12 output amplitude when changing # 68 input signal amplitude from 0 to 120 IRE (0.857 Vp-p). Then, compare to the plot in the step 2, calculate a point where a gradient changes (WPL1). Repeat the step 4 above by changing subaddress (19) data to (83) and (86). Calculate points where gradients change (WPL2, WPL3).
5.
80 ns
Figure A
# 12 output amplitude Data 87 WPL3 Data 86
Data 83 WPL2 Data 80 WPL1
# 68 input amplitude
Figure B
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TA1360AFG
Test Condition for Synchronization Block
Common Test Conditions for Synchronization Block: unless otherwise specified, VCC = 9 V, Ta = 25C, bus data; preset value, SW68 = A, SW53 = A, SW INPUT = B, SW44 = ON, SW41 = OPEN, SW40 = B, SW39a = B, SW39b = OPEN, SW37 = B
Note Characteristics Test Conditions Input signal A (as shown in the figure below) to TPA. Set subaddress (00) data to 82H. Monitor # 53 (Sync input) and #44 (AFC filter) waveforms. Measure phase difference (SPH).
HA01 Sync input horizontal 1. sync phase 2.
29.36 s
Signal A
0.285 V 0.593 s SPH
#44 waveform
HA02 HD input horizontal sync phase
1. 2. 3.
Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP50. Monitor #50 (Sync input) and #44 (AFC filter) waveforms. Measure phase difference (HDPH).
31.75 s
Signal B
1.5 V 2.35 s HDPH
#44 waveform
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Note Characteristics 1. 2. 3. 4. 5. 6. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP50 pin. Decrease signal B duty from 10% (to shorter negative polarity period) and measure signal B duty (HDDUTY1) when #50 input signal phase no longer locks with that of #37 (H-OUT). Increase signal B duty from 10% (to longer negative polarity period) and measure signal B duty (HDDUTY2) when #39 (FBP input) phase changes in relation to signal B. Further increase signal B duty (to longer negative polarity period) and measure signal B duty (HDDUTY3) when #50 input signal phase no longer locks with that of #37 (H-OUT). Decrease signal B duty from 90 % (to shorter negative polarity period) and measure signal B duty (HDDUTY4) when #39 (FBP input) phase changes in relation to signal B. Test Conditions
HA03 Polarity detection range
31.75 s
Signal B A B Duty = A/B x 100% (0 to 100%) HA04 Sync input threshold amplitude 1. 2. 3. 4. 5. 6.
1.5 V
Set subaddress (00) data to 82H, and TEST mode to 01. Connect variable power supply to #53 via 20-k resistor. Set variable power supply voltage to 0 V, and measure #53 voltage. (SYNC_TIP_00) Also check that #34 voltage is set to Low (GND level). Increase variable power supply voltage so that #34 voltage becomes High (VCC level). Measure #53 voltage. (SYNC_OFF_00) Calculate the following equation to determine SYNC input separation level at SYNC separation level is 00. VthS00 = (SYNC_OFF_00 - SYNC_TIP_00)/0.286 x 100 Change SYNC separation level to 01, 10, and 11. Calculate following equations to determine VthS01, VthS10, and VthS11. VthS01 = (SYNC_OFF_01 - SYNC_TIP_01)/0.286 x 100 VthS10 = (SYNC_OFF_10 - SYNC_TIP_10)/0.286 x 100 VthS11 = (SYNC_OFF_11 - SYNC_TIP_11)/0.286 x 100
53
1H
0.08H
40IRE (= 286 mVp-p)
Sync separation level Sync tip level
34 (SYNC output mode
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TA1360AFG
Note Characteristics 1. 2. 3. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP50. Increase signal B amplitude from 0 Vp-p. When #37 (H-OUT) phase locks with that of signal B, measure signal B amplitude VthHD. 31.75 s Test Conditions
HA05 HD input threshold amplitude
Signal B
VthDH 2.35 s
HA06 Horizontal picture phase adjustment variable range
1. 2. 3. 4.
Set subaddress (00) data to 40H. Input signal B (the figure is shown below) to TP50. Change subaddress (01) data from 80H to 00H, and measure phase change amount HSFT- of #39 (H-OUT) waveform. Change slave address (01) data from 80H to FEH, and measure phase change amount HSFT+ of #39 (H-OUT) waveform. 31.75 s
Signal B
1.5 V 2.35 s
#39 waveform Data: 00H HSFT- #39 waveform Data: 80H HSFT+ #39 waveform Data: FEH
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TA1360AFG
Note Characteristics 1. 2. 3. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP50. Connect external voltage to #40 (curve correction), and measure phase change amount (H#40) of #37 (H-OUT) output waveform at 1.5 V and 3.5 V. 31.75 s Test Conditions
HA07 Curve correction amount
Signal B
1.5 V 2.35 s
#37 waveform (#40 voltage; 1.5 V) H#40 #37 waveform (#40 voltage; 3.5 V)
HA08 Clamp pulse phase, width and level
1. 2. 3. 4. 5. 6.
Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP50. Measure #47 (SCP output) clamp pulse phase (CPS0), width (CPPW0), and output level (CPV0) in relation to signal B. Set subaddress (01) data to 81H, and repeat the step 3 above to measure (CPS1), (CPW1), and (CPV1). Apply no signal input to TP50. Measure #47 clamp pulse phase (CPS2), width (CPW2), and output level (CPV2) in relation to #39. 31.75 s
Signal B 2.35 s CPS0/1 #47 waveform
1.5 V
CPV0/1 CPW0/1
#39 waveform
CPS2
#47 waveform
CPV2 CPW2
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2003-01-21
TA1360AFG
Note Characteristics 1. 2. 3. 4. 5. Set subaddress (00) data to 40H. Set SW70 to C, SW68 to C, and SW39A to OPEN Input signal C (as the figure shown below) to #39 (FBP input). Measure #70 (BPH filter) black peak detection pulse phase (HBPS00a and HBPS00b) in relation to signal C. Set HBP-PHS 1/2 to (01), (10), and (11). Measure black peak detection pulse phase. Test Conditions
HA09 Black peak detection pulse phase and level
31.5 s 4.13 s 2V Signal C 0V HBPS**a HBPS**b
#70 waveform
HA10 FBP input threshold
1. 2. 3.
Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP50. Increase amplitude of FBP signal to be input to #39 (FBP input) from 0 Vp-p. When #37 (H-OUT) phase locks with that of signal B, measure #39 input amplitude VthFBP.
31.75 s
1.5 V 2.35 s
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2003-01-21
TA1360AFG
Note Characteristics 1. 2. No signal input. Measure T1 and T2 (as shown in the figure below) from #37 (H-OUT) output waveform when subaddress (00) data is 80H and A0H. Calculate duties (THA and THB) using the following equation: TH = T1/(T1 + T2) x 100 % T1 T2 Test Conditions
HB01 H-OUT pulse duty
#37 waveform
HB02 Horizontal free-run frequency
1. 2. 3.
Set SW44 to open. Set subaddress (00) data to 01H and measure horizontal free-run frequency (F15K) according to #37 (H-OUT) output waveform. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Measure horizontal free-run frequency F28K, F31K, F33K, F37K, and F45K as in the step 2 above. Set subaddress (00) data to 01H. Connect 10-k resistor between #44 and VCC. Measure horizontal frequency (F15KMIN) according to #37 (H-OUT) output waveform. Connect 68-k resistor between #44 and GND. Measure horizontal frequency (F15KMAX) according to #37 (H-OUT) output waveform. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the steps 2 and 3 above and measure horizontal frequencies F28KMIN, F28KMAX, F31KMIN, F31KMAX, F33KMIN, F33KMAX, F37KMIN, F37KMAX, F45KMIN, and F45KMAX. Set SW44 to open. Connect external power supply to TP44, and set subaddress (00) data to 01H. Apply V44 + 0.05 V, and V44 - 0.05 V to TP44. Measure frequencies FA and FB according to #37 (H-OUT) output waveform. Calculate frequency change rate (BH15K) using the following equation. BH15K = (FB - FA)/0.1 Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the step 2 above, and measure frequency change rate BH28K, BH31K, BH33K, BH37K, and BH45K Set SW37 to open. Measure voltage at High (V37H) and Low (V37L) of #37 (H-OUT) output waveform.
HB03 Horizontal oscillation frequency variable range
1. 2. 3. 4.
HB04 Horizontal oscillation control sensitivity
1. 2. 3.
4. HB05 H-OUT output voltage 1. 2.
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TA1360AFG
Note V01 Characteristics VP output pulse width, Vertical free-run (maximum pull-in range) 1. 2. 3. 4. Test Conditions Input signal D (shown in the figure below) to TP50, and signal E (shown in the figure below) to #39 (FBP input). Measure VP output pulse width (VPw) according to TP35 output waveform. Measure VP pull-in range (VPt0) according to TP35 output waveform. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure pull-in range VPt1, VPt2, VPt3, VPt4, VPt5, and VPt6 as in the step 3 above. 2.35 s 29.63 s Signal D (TP50 input signal) 5.6 s Signal E (#39 input waveform) 9V 4V
GND
#39 input waveform TP35 waveform VPw VPt
V02
Vertical minimum pull-in range
1. 2. 3.
Repeat the step 1 of Note #V01. Input signal F (shown in the figure below) to TP52. Increase signal-F cycle from 30 H. Measure the cycle (TVPULL) when phase locks with that of TP35.
Signal F (TP 52 waveform input) 3H TVPULL #39 input waveform TP 35 waveform
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Note V03 Characteristics Vertical black peak detection pulse 1. 2. 3. 4. Test Conditions Repeat the step 1 of Note #V01. Set SW70 to C, and SW68 to C. Input signal F (shown in the figure below) to TP52. Measure phase differences VBPP0E and VBPP0S according to #47 output waveform. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure phase differences VBPP1E, VBPP1S, VBPP2E, VBPP2S, VBPP3E, VBPP3S, VBPP4E, VBPP4S, VBPP5E, VBPP5S, VBPP6E, and VBPP6S as in the step 3 above.
Signal F (TP 52 waveform input) 3H 262.5H to 1125H #39 input waveform VBPPS VBPPE #70 waveform
V04
Vertical blanking stop 1. phase 2. 3.
Repeat the step 1 of Note #V01. Input signal F (shown in the figure below) to TP52. Set subaddress (03) data to 00H and F0H. Measure blanking stop phase VBLKMIN and VBLKMAX according to #12 output waveform.
Signal F (TP 52 waveform input) 3H 1125H #39 input waveform VBLK
#12 input waveform
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(1)
Video signal
63.5 s
Sine wave of frequency f0
(2)
Input signal 1
(3)
Input signal 2
Amplitude A
Sine wave of frequency f0
(4)
Input signal 3
Figure T-1
Signals for Text/Color Difference Signal 2
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TA1360AFG
63.5 s
20 s
20 s
20 s
20 ns
20 ns
(1) Input signal 4
50%
(2)
0% 10%
tPR
tPF
50%
90% 100% tPR R F tPF
(3)
0% 10%
50%
90% 100% R F
Figure T-2
Test Pulses for Text/Color Difference Signal 2
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Test Circuit
VCC (9 V) VCC (9 V) 9 3 k 1 F B 0.1 F SW53b 100 TP53b 5.1 k 3.9 k 0.01 F SW INPUT B TPD A A 0.1 F A TP61 SW60 B 0.1 F A TP60 TP55 SW64 TP64 A B 0.47 F 0.1 F A B SW63 0.1 F 15 k 15 k 15 k 470 10 11 12 13 #41 42 HVCO 41 H-FREQ SW2 100 A TP40b 1 F B C SW40 #40 10 k B FBP IN 39 10 k SW39a A #39 SW39B DEF/DAC GND 38 5.1 k H CURVE 40 CORRECTION H-OUT 37 #37 NC 36 1 k TP35 #35 71 DARK AREA DET FILTER TP71 B SW71 #71 72 NC DAC1 (SYNC OUT) 34 30 k 13 #34 1/2W 220 NC 33 50 k 7.5 k 1200 pF 14 15 16 C 3.9 k SW37 A B 10 11 12 TC4538BP 7 6 5 4 3 2 1 50 k 5.1 k 50 k 15.75 kHz 51 k 10 F 51 k 1000 pF 5.1 k 50 k 7.5 k 1200 pF 14 15 16 TC4538BP 8 7 6 5 4 3 2 1 50 k 31.5/33.75 kHz 51 k 10 F 51 k 1000 pF 5.1 k
CSBLA503KECZF30
TPC 10 F 75
30 k TP53
1 k TP44
TP52
TP50
TP49
TP47
SW61 B
100 F SW44
2 k
470
51 k 10 F 51 k
0.01 F
2.2 F
TPB
TPA 10 F 75
5.1 k 3.9 k
2 k
#64 64
#63 63
62 NC
#61 61 Cb2/Pb2 IN
#60 60 Cr2/Pr2 IN
#58 59 NC 58 COLOR LIMITER
#57 57 VSM FILTER
56 NC
#55 #54 #53 #52 #51 #50 #49 55 54 53 52 51 50 49 H-FREQ SW1 HD IN NC NC VD IN SYNC IN SCP IN
48 NC
#47 47 CP OUT
0.01 F
100
100
100
100
46 NC
45 DEF/DAC VCC
#44 44 AFC FILTER
#42 43 NC
LIGHT AREA DET FILTER
Y2 IN
65 Y/C GND TP66 A 0.1 F B SW66 #66 TP67 A 0.1 F 20 k 2 k
66 Cr1/Pr1 IN
67 Cb1/Pb1 IN B SW67 0.1 F #67 A B 68 Y1 IN SW68 0.1 F C 69 NC
9
8
1 F 100 k B A SW70 1 F 30 pF 20 k 0.47 F #70 A
70 BPH FILTER
VP OUT 35
TA1360AFG
73 NC 10 F SW74 0.01 F #74 100 F TP77 1 k SW77 0.01 F #77 TP78 100 k YS2 (ANALOG OSD) YS3 (ANALOG RGB) DAC2 (ACP PULSE) ANALOG OSD G IN ANALOG OSD R IN ANALOG OSD B IN #78 #79 79 YM/P-MUTE/BLK 80 Ys1 (ANALOG OSD)
NC 32 I2L VDD 31 #31 0.1 F 470 #30
74 APL FILTER
2.0 V TP30
75 Y/C VCC #75 76 NC
SCL 30
NC 29 470 #28 9 TP28 10 11 TP26 12 13 50 k 7.5 k 1200 pF 14 15 16 TC4538BP 7 6 5 4 3 2 1 8
77 VSM OUT
2
SDA 28
78 ABCL IN
I L GND 27 SW26 A 0.1 F B SW25 #26 A ANALOG G IN 25 0.1 F B #25 ANALOG B IN 26
RGB VCC
#80
RGB GND
ANALOG R IN
TP25
G OUT
R OUT
G S/H
R S/H
B S/H
B OUT
IK IN
NC
NC
NC
NC
NC
1
2
3 #4
4 0.01 F
5 #6
6 #7 0.01 F
7 #8 0.01 F
8
9
10
11
NC
12 13 14 #12 #13 #14 100 100 100
15 #16
NC
16
17 #18 0.01 F
18 #19
19 0.1 F
20 #21
21 0.1 F
22 #23
NC
23 #24
24 0.1 F
0.1 F A B SW19
B SW18
B SW21
300 pF
100 F
B SW24
A
A
10 k
6.8 V
TP18
TP19
TP21
#1
#2 10 k 10 k
10 k
10 k
10 k
10 k
10 k
TP24
A
1000 pF
45 kHz
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Application Circuit
5.1 k 3.9 k
5.1 k 3.9 k
5.1 k 3.9 k
5.1 k 3.9 k
VCC 1 k 47 H VCC
10 F Y2-IN 75
Cb2/Pb2 IN 10 F 75 1 k
Cr2/Pr2 IN 10 F 75 1 k
10 F SYNC IN 1 k 75
1 k
0.1 F
CSBLA503KECZF30
1.5 k
560
A
CP-OUT
SCP-IN
100 F 3 k 1 F
B
HD-IN
VD-IN
0.01 F
F
0.1 F
0.1 F
0.1 F
0.01 F
2.2 F
0.1 F
5.1 k 3.9 k
0.47 F
M
M
10 F Cr1/Pr1 IN 75
64 LIGHT AREA DET FILTER 1 k
63 Y2 IN
62 NC
61 Cb2/Pb2 IN
M
60 Cr2/Pr2 IN
59 NC
58 COLOR LIMITER
57 VSM FILTER
56 NC
55 H-FREQ SW1
54 NC
53 SYNC IN
52 VD IN
51 NC
50 HD IN
49 SCP IN
48 NC
47 CP OUT
46 NC
45 DEF/DAC VCC
44 AFC FILTER
M 0.01
470
43 NC
42 HVCO
41 H-FREQ SW2
65 Y/C GND 5.1 k 3.9 k
H CURVE 40 CORRECTION FBP IN 39 10 k
CURVE CORR
10 F Cb1 /Pb1 IN 75
M 0.1
F F
66 Cr1/Pr1 IN 67 Cb1/Pb1 IN 68 Y1 IN
FBP-IN
1 k
M 0.1
DEF/DAC GND 38 1 k
M 0.1
F
H-OUT 37 H-OUT
5.1 k 3.9 k
10 F Y1 IN 75
69 NC
NC 36
1 k
1 F 0.47 F
70 BPH FILTER
VP OUT 35 30 k
VP-OUT
71 DARK AREA DET FILTER
DAC1 (SYNC OUT) 34
DAC1-OUT 72 NC
TA1360AFG
NC 33
73 NC 2.2 F 74 APL FILTER 47 H 0.01 F 75 Y/C VCC 76 NC VSM OUT 100 k 0.01 F ABCL 100 k YS3 (ANALOG RGB) YS2 (ANALOG OSD) YM 79 YM/P-MUTE/BLK 80 Ys1 (ANALOG OSD) ANALOG OSD B IN DAC2 (ACP PULSE) ANALOG OSD G IN ANALOG OSD R IN 78 ABCL IN 77 VSM OUT
2
NC 32 I2L VDD 31 0.01 F SCL 30 470 SCL 2.0 V
100 F NC 29
SDA 28
470
SDA
I L GND 27
ANALOG B IN 26 ANALOG R IN
0.1 F 0.1 F
ANALOG B IN
RGB GND
G OUT
R OUT
G S/H
R S/H
B S/H
B OUT
IK IN
RGB VCC
Ys1
ANALOG G IN 25
ANALOG G IN
NC
NC
NC
NC
1
2
NC
3 2.2 F
4
5 2.2 F
6 2.2 F
7
8
9
10
11
NC
12
13
14
15
NC
16
17 0.01 F
18 0.1 F
19 0.1 F
20
21 0.1 F
22
NC
23
24 0.1 F
100 F
30 k
300 pF
30 k
M:
Mylar capacitor
Ys2
Ys3
DAC2-OUT
ANALOG R-IN
6.8 V
47 H
Application of H-FREQ switching (31.5 k/33.75 k/45 kHz) Tr. H-FREQ 31.5 kHz 33.75 kHz 45 kHz A L L H B L H * Pin 55 voltage Pin 41 voltage 9V 9V 9V 6V 3V 0V
100
100
100
OSD G-IN
OSD R-IN
IK-IN
R OUT
G OUT
B OUT
OSD B-IN
*: Don't care
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TA1360AFG
ACB Application Circuit
+B
CRT
CRT
CRT
R
G
B
IK IN 51~330 pF 6.8 V Z CLAMP 8 1 Vp-p R G B 0~3.0 V (DC) 20~51 k
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2003-01-21
TA1360AFG
Package Dimensions
Weight: 1.6 g (typ.)
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2003-01-21
TA1360AFG
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2003-01-21

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